AT90PWM2 datasheet(105/365 Pages) ATMEL

105 / 365 page

105

AT90PWM2/3

4317B–AVR–02/05

Figure 42. 16-bit Timer/Counter Block Diagram(1)

Note:

1. Refer to

Table on page 5 for Timer/Counter1 pin placement and description.

Registers

The Timer/Counter (TCNTn), Output Compare Registers (OCRnx), and Input Capture

accessing the 16-bit registers. These procedures are described in the section “Access-

ing 16-bit Registers” on page 106. The Timer/Counter Control Registers (TCCRnx) are

8-bit registers and have no CPU access restrictions. Interrupt requests (abbreviated to

Int.Req. in the figure) signals are all visible in the Timer Interrupt Flag Register (TIFRn).

All interrupts are individually masked with the Timer Interrupt Mask Register (TIMSKn).

TIFRn and TIMSKn are not shown in the figure.

The Timer/Counter can be clocked internally, via the prescaler, or by an external clock

source on the Tn pin. The Clock Select logic block controls which clock source and edge

the Timer/Counter uses to increment (or decrement) its value. The Timer/Counter is

inactive when no clock source is selected. The output from the Clock Select logic is

referred to as the timer clock (clk

Tn).

The double buffered Output Compare Registers (OCRnx) are compared with the

Timer/Counter value at all time. The result of the compare can be used by the Waveform

Generator to generate a PWM or variable frequency output on the Output Compare pin

(OCnx). See “Output Compare Units” on page 112.. The compare match event will also

set the Compare Match Flag (OCFnx) which can be used to generate an Output Com-

pare interrupt request.

Clock Select

Timer/Counter

OCRnA

OCRnB

ICRn

TCNTn

Waveform

Generation

Waveform

Generation

OCnA

OCnB

Noise

Canceler

ICPnB

Fixed

TOP

Values

Edge

Detector

Control Logic

= 0

TOP

BOTTOM

Count

Clear

Direction

TOVn

(Int.Req.)

OCnA

(Int.Req.)

OCnB

(Int.Req.)

ICFn (Int.Req.)

TCCRnA

TCCRnB

Edge

Detector

( From Prescaler )

clk

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