AT90PWM2 datasheet(48/365 Pages) ATMEL

48 / 365 page

AT90PWM2/3

4317B–AVR–02/05

When the BOD is enabled, and V

CC decreases to a value below the trigger level (VBOT-

in Figure 21), the Brown-out Reset is immediately activated. When V

CC increases above

the trigger level (V

BOT+ in Figure 21), the delay counter starts the MCU after the Time-

out period t

TOUT has expired.

The BOD circuit will only detect a drop in V

CC if the voltage stays below the trigger level

for longer than t

BOD given in Table 16.

Figure 21. Brown-out Reset During Operation

Watchdog Reset

When the Watchdog times out, it will generate a short reset pulse of one CK cycle dura-

tion. On the falling edge of this pulse, the delay timer starts counting the Time-out period

TOUT. Refer to page 50 for details on operation of the Watchdog Timer.

Figure 22. Watchdog Reset During Operation

MCU Status Register –

MCUSR

The MCU Status Register provides information on which reset source caused an MCU

reset.

• Bit 3 – WDRF: Watchdog Reset Flag

This bit is set if a Watchdog Reset occurs. The bit is reset by a Power-on Reset, or by

writing a logic zero to the flag.

VCC

RESET

TIME-OUT

INTERNAL

RESET

VBOT-

VBOT+

tTOUT

Bit

–

WDRF

BORF

EXTRF

PORF

MCUSR

Read/Write

R/W

Initial Value

See Bit Description

AT90PWM2 Datasheet(PDF) 48 Page - ATMEL Corporation

AT90PWM2 Datasheet(HTML) 48 Page - ATMEL Corporation

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