| Electronic Components Datasheet Search |
|
AT90PWM2 Datasheet(PDF) 35 Page - ATMEL Corporation |
|
|
|||||||||||||||||||||||||||||
AT90PWM2 Datasheet(HTML) 35 Page - ATMEL Corporation |
|
35 / 365 page ![]() 35 AT90PWM2/3 4317B–AVR–02/05 The PLL is locked on the RC Oscillator and adjusting the RC Oscillator via OSCCAL Register will adjust the fast peripheral clock at the same time. However, even if the pos- sibly divided RC Oscillator is taken to a higher frequency than 1 MHz, the fast peripheral clock frequency saturates at 70 MHz (worst case) and remains oscillating at the maxi- mum frequency. It should be noted that the PLL in this case is not locked any more with the RC Oscillator clock. Therefore it is recommended not to take the OSCCAL adjustments to a higher fre- quency than 1 MHz in order to keep the PLL in the correct operating range. The internal PLL is enabled only when the PLLE bit in the register PLLCSR is set. The bit PLOCK from the register PLLCSR is set when PLL is locked. Both internal 1 MHz RC Oscillator and PLL are switched off in Power-down and Standby sleep modes. Figure 15. PCK Clocking System PLL Control and Status Register – PLLCSR • Bit 7..3 – Res: Reserved Bits These bits are reserved bits in the AT90PWM2/3 and always read as zero. • Bit 2 – PLLF: PLL Factor The PLLF bit is used to select the division factor of the PLL. If PLLF is set, the PLL output is 64Mhz. If PLLF is clear, the PLL output is 32Mhz. • Bit 1 – PLLE: PLL Enable When the PLLE is set, the PLL is started and if not yet started the internal RC Oscillator is started as PLL reference clock. If PLL is selected as a system clock source the value for this bit is always 1. • Bit 0 – PLOCK: PLL Lock Detector When the PLOCK bit is set, the PLL is locked to the reference clock, and it is safe to enable CLK PLL for PSC. After the PLL is enabled, it takes about 100 ms for the PLL to lock. 8 MHz RC OSCILLATOR OSCCAL XTAL1 XTAL2 OSCILLATORS DIVIDE BY 8 DIVIDE BY 2 CK PLL 64x PLLE Lock Detector PLOCK SOURCE PLLF DIVIDE BY 4 CLK PLL Bit 765 4321 0 $29 ($29) – – – – – PLLF PLLE PLOCK PLLCSR Read/Write R R R R R R/W R/W R Initial Value 0 0 0 0 0 0 0/1 0 |
|
Link URL |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link to Datasheet | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |