AT90PWM2 datasheet(46/365 Pages) ATMEL

46 / 365 page

AT90PWM2/3

4317B–AVR–02/05

Power-on Reset

A Power-on Reset (POR) pulse is generated by an On-chip detection circuit. The detec-

tion level is defined in Table 14. The POR is activated whenever V

CC is below the

detection level. The POR circuit can be used to trigger the start-up Reset, as well as to

detect a failure in supply voltage.

A Power-on Reset (POR) circuit ensures that the device is reset from Power-on. Reach-

ing the Power-on Reset threshold voltage invokes the delay counter, which determines

how long the device is kept in RESET after V

CC rise. The RESET signal is activated

again, without any delay, when V

CC decreases below the detection level.

Figure 18. MCU Start-up, RESET Tied to V

Figure 19. MCU Start-up, RESET Extended Externally

External Reset

An External Reset is generated by a low level on the RESET pin. Reset pulses longer

than the minimum pulse width (see Table 14) will generate a reset, even if the clock is

not running. Shorter pulses are not guaranteed to generate a reset. When the applied

signal reaches the Reset Threshold Voltage – VRST – on its positive edge, the delay

counter starts the MCU after the Time-out period – tTOUT – has expired.

RESET

TIME-OUT

INTERNAL

RESET

TOUT

POT

RST

RESET

TIME-OUT

INTERNAL

RESET

TOUT

POT

RST

VCC

AT90PWM2 Datasheet(PDF) 46 Page - ATMEL Corporation