AT90PWM2 datasheet(34/365 Pages) ATMEL

34 / 365 page

AT90PWM2/3

4317B–AVR–02/05

When this Oscillator is selected, start-up times are determined by the SUT Fuses as

shown in Table 8 on page 34.

Note:

1. If the RSTDISBL fuse is programmed, this start-up time will be increased to

14CK + 4.1 ms to ensure programming mode can be entered.

The device is shipped with this option selected.

Oscillator Calibration Register

– OSCCAL

• Bits 7..0 – CAL7..0: Oscillator Calibration Value

The Oscillator Calibration Register is used to trim the Calibrated Internal RC Oscillator

to remove process variations from the oscillator frequency. The factory-calibrated value

is automatically written to this register during chip reset, giving an oscillator frequency of

8.0 MHz at 25°C. The application software can write this register to change the oscillator

frequency. The oscillator can be calibrated to any frequency in the range 7.3 - 8.1 MHz

within ±1% accuracy. Calibration outside that range is not guaranteed.

Note that this oscillator is used to time EEPROM and Flash write accesses, and these

write times will be affected accordingly. If the EEPROM or Flash are written, do not cali-

brate to more than 8.8 MHz. Otherwise, the EEPROM or Flash write may fail.

The CAL7 bit determines the range of operation for the oscillator. Setting this bit to 0

gives the lowest frequency range, setting this bit to 1 gives the highest frequency range.

The two frequency ranges are overlapping, in other words a setting of OSCCAL = 0x7F

gives a higher frequency than OSCCAL = 0x80.

The CAL6..0 bits are used to tune the frequency within the selected range. A setting of

0x00 gives the lowest frequency in that range, and a setting of 0x7F gives the highest

frequency in the range. Incrementing CAL6..0 by 1 will give a frequency increment of

less than 2% in the frequency range 7.3 - 8.1 MHz.

PLL

To generate high frequency and accurate PWM waveforms, the ‘PSC’s need high fre-

quency clock input. This clock is generated by a PLL. To keep all PWM accuracy, the

frequency factor of PLL must be configurable by software. With a system clock of 8

MHz, the PLL output is 32Mhz or 64Mhz.

Internal PLL for PSC

The internal PLL in AT90PWM2/3 generates a clock frequency that is 64x multiplied

from nominally 1 MHz input. The source of the 1 MHz PLL input clock is the output of the

internal RC Oscillator which is divided down to 1 MHz. See the Figure 15 on page 35.

Table 8. Start-up times for the internal calibrated RC Oscillator clock selection

Power Conditions

Start-up Time from Power-

down and Power-save

Additional Delay from

Reset (V

CC = 5.0V)

SUT1..0

BOD enabled

6 CK

14CK

(1)

Fast rising power

6 CK

14CK + 4.1 ms

Slowly rising power

6 CK

14CK + 65 ms

(2)

Reserved

Bit

765

432

CAL7

CAL6

CAL5

CAL4

CAL3

CAL2

CAL1

CAL0

OSCCAL

Read/Write

R/W

Initial Value

Device Specific Calibration Value

AT90PWM2 Datasheet(PDF) 34 Page - ATMEL Corporation

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