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AT90PWM2 Datasheet(PDF) 30 Page - ATMEL Corporation |
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AT90PWM2 Datasheet(HTML) 30 Page - ATMEL Corporation |
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30 / 365 page ![]() 30 AT90PWM2/3 4317B–AVR–02/05 System Clock Clock Systems and their Distribution Figure 13 presents the principal clock systems in the AVR and their distribution. All of the clocks need not be active at a given time. In order to reduce power consumption, the clocks to unused modules can be halted by using different sleep modes, as described in “Power Management and Sleep Modes” on page 39. The clock systems are detailed below. Figure 13. Clock Distribution CPU Clock – clk CPU The CPU clock is routed to parts of the system concerned with operation of the AVR core. Examples of such modules are the General Purpose Register File, the Status Reg- ister and the data memory holding the Stack Pointer. Halting the CPU clock inhibits the core from performing general operations and calculations. I/O Clock – clk I/O The I/O clock is used by the majority of the I/O modules, like Timer/Counters, SPI, USART. The I/O clock is also used by the External Interrupt module, but note that some external interrupts are detected by asynchronous logic, allowing such interrupts to be detected even if the I/O clock is halted. Flash Clock – clk FLASH The Flash clock controls operation of the Flash interface. The Flash clock is usually active simultaneously with the CPU clock. PLL Clock – clk PLL The PLL clock allows the PSC modules to be clocked directly from a 64/32 MHz clock. A 16 MHz clock is also derived for the CPU. General I/O Modules ADC CPU Core RAM clk I/O AVR Clock Control Unit clk CPU Flash and EEPROM clk FLASH clk ADC Source Clock Watchdog Timer Watchdog Oscillator Reset Logic Clock Multiplexer Watchdog Clock Calibrated RC Oscillator (Crystal Oscillator) External Clock PSC0/1/2 PLL CLK PLL |
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