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AT90PWM2 Datasheet(PDF) 23 Page - ATMEL Corporation |
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AT90PWM2 Datasheet(HTML) 23 Page - ATMEL Corporation |
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23 / 365 page  23 AT90PWM2/3 4317B–AVR–02/05 EEPROM Data Memory The AT90PWM2/3 contains 512 bytes of data EEPROM memory. It is organized as a separate data space, in which single bytes can be read and written. The EEPROM has an endurance of at least 100,000 write/erase cycles. The access between the EEPROM and the CPU is described in the following, specifying the EEPROM Address Registers, the EEPROM Data Register, and the EEPROM Control Register. For a detailed description of SPI and Parallel data downloading to the EEPROM, see “Serial Downloading” on page 304 , and “Parallel Programming Parameters, Pin Map- ping, and Commands” on page 292 respectively. EEPROM Read/Write Access The EEPROM Access Registers are accessible in the I/O space. The write access time for the EEPROM is given in Table 2. A self-timing function, how- ever, lets the user software detect when the next byte can be written. If the user code contains instructions that write the EEPROM, some precautions must be taken. In heavily filtered power supplies, V CC is likely to rise or fall slowly on power-up/down. This causes the device for some period of time to run at a voltage lower than specified as minimum for the clock frequency used. See “Preventing EEPROM Corruption” on page 27.for details on how to avoid problems in these situations. In order to prevent unintentional EEPROM writes, a specific write procedure must be fol- lowed. Refer to the description of the EEPROM Control Register for details on this. When the EEPROM is read, the CPU is halted for four clock cycles before the next instruction is executed. When the EEPROM is written, the CPU is halted for two clock cycles before the next instruction is executed. The EEPROM Address Registers – EEARH and EEARL • Bits 15..9 – Reserved Bits These bits are reserved bits in the AT90PWM2/3 and will always read as zero. • Bits 8..0 – EEAR8..0: EEPROM Address The EEPROM Address Registers – EEARH and EEARL specify the EEPROM address in the 512 bytes EEPROM space. The EEPROM data bytes are addressed linearly between 0 and 511. The initial value of EEAR is undefined. A proper value must be writ- ten before the EEPROM may be accessed. The EEPROM Data Register – EEDR • Bits 7..0 – EEDR7.0: EEPROM Data For the EEPROM write operation, the EEDR Register contains the data to be written to the EEPROM in the address given by the EEAR Register. For the EEPROM read oper- Bit 15 14 13 12 11 10 9 8 – – – – – – – EEAR8 EEARH EEAR7 EEAR6 EEAR5 EEAR4 EEAR3 EEAR2 EEAR1 EEAR0 EEARL 765 4 3 2 1 0 Read/Write RRRR R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 X X X X XX XX X X X X Bit 765 432 10 EEDR7 EEDR6 EEDR5 EEDR4 EEDR3 EEDR2 EEDR1 EEDR0 EEDR Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 000 000 00 |
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