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TPS2521 Datasheet(PDF) 6 Page - Texas Instruments

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Part # TPS2521
Description  TPS2521xx, 2.7 - 5.7 V, 4 A, 31-m廓 True Reverse Current Blocking eFuse with Input Reverse Polarity Protection
PDF  47 Pages
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Manufacturer  TI [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI - Texas Instruments

TPS2521 Datasheet(HTML) 6 Page - Texas Instruments

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7.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
Parameter
Pin
MIN
MAX
UNIT
VIN
Input Voltage Range
IN
2.7
5.7 (1)
V
VOUT
Output Voltage Range
OUT
min (23, VIN + 20)
V
VEN/UVLO
Enable Pin Voltage Range
EN/UVLO
5 (2)
V
VdVdT
dVdT Capacitor Voltage Rating
dVdt
VIN + 5 V
V
VPGTH
PGTH Pin Voltage Range
PGTH
5 (3)
V
VPG
PG Pin Voltage Range
PG
5 (3)
V
VITIMER
ITIMER Pin Capacitor Voltage Rating
ITIMER
4
V
RILM
ILM Pin Resistance
ILM
750
6650
Ω
IMAX
Continuous Switch Current, TJ ≤ 125 ℃
IN to OUT
4
A
TJ
Junction temperature
–40
125
°C
(1)
The input operating voltage should be limited to the selected Output Voltage Clamp threshold as listed in the Electrical Characteristics
section
(2)
For supply voltages below 5V, it is okay to pull up the EN pin to IN directly. For supply voltages greater than 5V or systems which can
be exposed to reverse polarity on input supply, it is recommended to use a pull-up resistor with a minimum value of 350 kΩ.
(3)
For systems which can be exposed to reverse polarity on input supply, if this pin is referred to input supply, it is recommended to use a
pull-up resistor with a minimum value of 350 kΩ to limit the current through the pin.
7.4 Thermal Information
THERMAL METRIC (1)
TPS2521xx
UNIT
RPW (QFN)
10 PINS
RθJA
Junction-to-ambient thermal resistance
41.7 (2)
°C/W
74.5 (3)
°C/W
ΨJT
Junction-to-top characterization parameter
1
°C/W
ΨJB
Junction-to-board characterization parameter
20 (2)
°C/W
27.6 (3)
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
(2)
Based on simulations conducted with the device mounted on a custom 4-layer PCB (2s2p) with 8 thermal vias under device
(3)
Based on simulations conducted with the device mounted on a JEDEC 4-layer PCB (2s2p) with no thermal vias under device
TPS2521
SLVSFX8 – MARCH 2021
www.ti.com
6
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Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: TPS2521



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