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FUNCTIONAL DESCRIPTION

Zero ppm Audio and Video System Clock Generation and Divider Setting

CDCE906

SCAS814 – NOVEMBER 2005

SSC2

SSC1

SSC0

Function

1

0

1

SSC Modulation Amount 1.5% (down spread)

1

1

0

SSC Modulation Amount 2% (down spread)

1

1

1

SSC Modulation Amount 3% (down spread)

Byte 25, Bit [7]: Permanently Lock EEPROM-Data

EELOCK

0

No

Yes

1

Yes

(1)

If this bit is set, the actual data in the EEPROM will be permanently locked. There is no further programming possible, even this bit is set

low. Data, however can still be written via SMBUS to the internal register to change device function on the fly. But new data no longer

can be stored into the EEPROM.

(2)

Unless customer specific setting.

BC6

BC5

BC4

BC3

BC2

BC1

BC0

No. of Bytes

0

0

0

0

0

0

0

Not allowed

0

0

0

0

0

0

1

1

0

0

0

0

0

1

0

2

0

0

0

0

0

1

1

3

•

•

•

0

0

1

1

0

1

1

27

Yes

•

•

•

1

1

1

1

1

0

1

125

1

1

1

1

1

1

0

126

1

1

1

1

1

1

1

127

(1)

Defines the number of Bytes, which will be sent from this device at the next Block Read protocol.

(2)

Unless customer specific setting.

EEWRITE

Starts EEPROM Write Cycle

0

No

Yes

1

Yes

(1)

The EEPROM WRITE cycle is initiated with the rising edge of the EEWRITE-Bit. A static level high does not trigger an EEPROM WRITE

cycle. This bit stays high until the user reset it to low (it will not automatically be reset after the programming has been completed).

Therefore, to initiate an EEPROM WRITE cycle, it is recommended to send a zero-one sequence to the EEWRITE bit in Byte 26.

During EEPROM programming, no data are allowed to be sent to the device via the SMBus until the programming sequence has been

completed. Data, however, can be readout during the programming sequence (Byte Read or Block Read). The programming status can

be monitored by readout EEPIP, Byte 24–Bit 7. If EELOCK is set, no EEPROM programming will be possible.

(2)

Unless customer specific setting.

The CDCE906 is ideally suited for audio and video applications. It consists of a triple PLL clock generator which

generates up to six audio, video and system clocks from i.e. a 27-MHz master clock. The output frequencies are

programmable to meet different application requirements. The master clock can be either a crystal oscillator or

an external input clock signal. The CDCE906 provides a very low jitter, high accuracy clock with zero ppm for the

common audio and video clocks. The following table shows the system clocks versus the standard sampling

frequency and the corresponding divider settings.

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