CDCE906 datasheet(27/33 Pages) TI

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Performance Data: Output Skew, Jitter, Cross Coupling, Noise Rejection (Spur-Suppression),

Output Skew

Jitter Performance

CDCE906

SCAS814 – NOVEMBER 2005

and Phase Noise

Skew is an important parameter for clock distribution circuits. It is defined as the time difference between outputs

that are driven by the same input clock. Table 5 shows the output skew (tsk(o)) of the CDCE906 for high-to-low

and low-to-high transitions over the entire range of supply voltages, operating temperature and output voltage

swing.

Table 5. Output Skew

PARAMETER

Vccout

TYP

MAX

UNIT

2.5 V

130

250

tsk(o)

3.3 V

130

200

Jitter is a major parameter for PLL-based clock driver circuits. This becomes important as speed increases and

timing budget decreases. The PLL and internal circuits of CDCE906 are designed for lowest jitter. The

peak-to-peak period jitter is only 60 ps (typical). Table 6 gives the peak-to-peak and rms deviation of

cycle-to-cycle jitter, period jitter and phase jitter as taken during characterization.

Table 6. Jitter Performance of CDCE906

PARAMETER

fout

TYP(1)

MAX(1)

UNIT

Peak-Peak

rms

Peak-Peak

rms

(one sigma)

tjit(cc)

50 MHz

–

133 MHz

–

245.76 MHz

–

tjit(per)

50 MHz

133 MHz

245.76 MHz

tjit(phase)

50 MHz

730

840

115

133 MHz

930

130

1310

175

245.76 MHz

720

930

125

(1)

All typical and maximum values are at VCC = 3.3 V, temperature = 25°C, Vccout = 3.3 V; one output is switching, data taken over several

10000 cycles.

Figure 22, Figure 23, and Figure 24 show the relationship between cycle-to-cycle jitter, period jitter, and phase

jitter over 10000 samples. The jitter varies with a smaller or wider sample window. The cycle-to-cycle jitter and

period jitter show the measured value whereas the phase jitter is the accumulated period jitter.

Cycle-to-Cycle jitter (tjit(cc)) is the variation in cycle time of a clock signal between adjacent cycles, over a random

sample of adjacent cycle pairs. Cycle-to-cycle jitter will never be greater than the period jitter. It is also known as

adjacent cycle jitter.

CDCE906 Datasheet(PDF) 27 Page - Texas Instruments

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