VT8601 Apollo ProMedia
Revision 1.3 September 8, 1999
-102
VGA Extended Registers
7HFKQRORJLHV ,QF
:H&
:H&RRQQHFW
QQHFW
CR9D – Capture Control 2...............................................RW
7
Capture DTV / CCIR Format Select
0
CCIR .....................................................default
1DTV
6-4
Horizontal Filter Tap
0xx Bypass ....................................................default
100 2 Tap
101 3Tap
110 5 Tap
111 9 Tap
3
UV Swap
0
Normal ...................................................default
1Swap
2
YUV Swap
0
Normal ...................................................default
1Swap
1
Philips 9051 Format Select
0
Normal ...................................................default
1
UV9051 Format
0
TV 8-Bit Control
0
16-bit capture input ................................default
1
8-bit capture input
CR9E – Capture Control 3...............................................RW
7-6
Capture Input Data Mode
00 YUV 4:2:2..............................................default
01 YUV 4:1:1
10 RGB 565
11 -reserved-
5
CGS Clock Double
0
Normal ...................................................default
1
Double
4
Capture Clock Polarity
0
Normal ...................................................default
1
Invert
3-2
Capture Clock Delay Select
00 No delay .................................................default
01 3 ns
10 6 ns
11 9 ns
1Hsync Delay
0
Normal ...................................................default
1
Delay
0
PCI Frame Start and Busy
0
PCI Video Not Busy...............................default
1
PCI Video Busy
CR9F – Capture Control 4 .............................................. RW
7-6
Capture Interrupt Source
00 Capture vsync ........................................ default
01 Capture even field
10 Capture odd field
11 Capture blank
5
IBM MPEG2 Mode Enable
0
Normal ................................................... default
1
IBM MPEG2 Mode
4
Production Test Mode for Capture
0
Normal ................................................... default
1
For test purposes, the ESYNC# pin is used
instead of capture Vsync and EDCLK# is used
instead of external CLK
3-1
Capture Clock Divide Factor Select
Capture clock divide factor when the internal pixel
clock is source:
000 Divide by 1 ............................................ default
001 Divide by 2
010 Divide by 3
011 Divide by 4
100 Divide by 5
101 Divide by 6
110 Select 14.318 MHz Clock
111 Select 28.636 MHz Clock
0
Capture Clock Select
0
Use external capture clock..................... default
1
Use internal pixel clock divided by the factor
above
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