ADPD107 datasheet(36/66 Pages) AD

36 / 66 page

ADPD105/ADPD106/ADPD107

Data Sheet

Rev. A | Page 36 of 66

SLOT A

SLOT B

SLOT A

SLEEP

0x02

0x05

0x06

0x07

0x0F

Figure 41. Optional Timing Signals Available on GPIOx—Register 0x0B, Bits[12:8] or Bits[4:0] = 0x02, 0x05, 0x06, 0x07, and 0x0F

SLOT A/B

0x02

0x0D

0x0E

0x0C

SLEEP

Figure 42. Optional Timing Signals Available on GPIOx—Register 0x0B, Bits[12:8] or Bits[4:0] = 0x02, 0x0C, 0x0D, and 0x0E

ADPD103 Backward Compatibility

Setting Register 0x0B = 0 provides backward compatibility to

the ADPD103. The GPIO0 pin mirrors the functionality of the

ADPD103 INT pin. The GPIO1 pin mirrors the functionality of

the ADPD103 PDSO pin.

Interrupt Function

Setting Register 0x0B, Bits[12:8] or Bits[4:0] = 0x01 configures

the respective pin to perform the interrupt function as defined

by the settings in Register 0x01.

Sample Timing

Setting Register 0x0B, Bits[12:8] or Bits[4:0] = 0x02 configures

the respective pin to provide a signal that asserts at the beginning

of the first time slot of the current sample and deasserts at the

end of the last time slot of the current sample. For example, if

both time slots are enabled, this signal asserts at the beginning

of Time Slot A and deasserts at the end of Time Slot B. If only a

single time slot is enabled, the signal asserts at the beginning of

the enabled time slot and deasserts at the end of this same time slot.

Pulse Outputs

Three options are available to provide a copy of the LED pulse

outputs. Setting Register 0x0B, Bits[12:8] or Bits[4:0] = 0x05

provides a copy of the Time Slot A LED pulses on the respective

pin. A setting of 0x06 provides the Time Slot B pulses, and a

setting of 0x07 provides the pulse outputs of both time slots.

Output Data Cycle Signal

There are three options available to provide a signal that

indicates when the output data is written to the output data

registers or to the FIFO. Setting Register 0x0B, Bits[12:8] or

Bits[4:0] = 0x0C provides a signal that indicates that a data

value is written for Time Slot A. A setting of 0x0D provides a

signal that indicates that a data value is written for Time Slot B,

and 0x0E provides a signal to indicate that a value is written for

either time slot. The signal asserts at the end of the time slot,

when the output data is already written, and deasserts at the

start of the subsequent sample. This timing signal is especially

useful in situations where the FIFO is being used. For example,

one of the GPIOx pins can be configured to provide an interrupt

after the FIFO reaches the FIFO threshold set in Register 0x06,

Bits[13:8], while the other GPIOx pin can be configured to

provide the output data cycle signal. This signal can be used to

trigger a peripheral device, such as an accelerometer, so that

time aligned signals are provided to the processor.

ADPD107 Datasheet(PDF) 36 Page - Analog Devices

ADPD107 Datasheet(HTML) 36 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66

Datasheet Download

Link URL