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ADPD107 Datasheet(PDF) 11 Page - Analog Devices |
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ADPD107 Datasheet(HTML) 11 Page - Analog Devices |
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11 / 66 page ![]() Data Sheet ADPD105/ADPD106/ADPD107 Rev. A | Page 11 of 66 Table 7. SPI Timing Specifications Parameter Symbol Test Conditions/Comments Min Typ Max Unit SPI PORT SCLK Frequency fSCLK 10 MHz Minimum Pulse Width High tSCLKPWH 20 ns Low tSCLKPWL 20 ns CS Setup Time t CSS CS setup to SCLK rising edge 10 ns Hold Time t CSH CS hold from SCLK rising edge 10 ns Pulse Width High t CSPWH CS pulse width high 10 ns MOSI ns Setup Time tMOSIS MOSI setup to SCLK rising edge 10 ns Hold Time tMOSIH MOSI hold from SCLK rising edge 10 MISO Output Delay tMISOD MISO valid output delay from SCLK falling edge 20 ns CS tCSS tMOSIS tMOSIH tMISOD tSCLKPWH tSCLKPWL tCSH tCSPWH SCLK MISO MOSI Figure 4. SPI Timing Diagram |
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