ADPD107 datasheet(61/66 Pages) AD

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Data Sheet

ADPD105/ADPD106/ADPD107

Rev. A | Page 61 of 66

Address

Data

Bit

Default

Access

Name

Description

0x0D

[15:0]

0x0000

R/W

SLAVE_ADDRESS_KEY

Enable changing the I2C address using Register 0x09.

0x04AD: enable address change always.

0x44AD: enable address change if GPIO0 is high.

0x84AD: enable address change if GPIO1 is high.

0xC4AD: enable address change if both GPIO0 and GPIO1 are high.

0x0F

[15:1]

0x0000

Reserved

Write 0x0000.

0x0

R/W

SW_RESET

Software reset. Write 0x1 to reset the device. This bit clears itself after a

reset. For I2C communications, this command returns an acknowledge

and the device subsequently returns to standby mode with all registers

reset to the default state.

0x10

[15:2]

0x0000

R/W

Reserved

Write 0x000.

[1:0]

0x0

R/W

Mode

Determines the operating mode of the ADPD105/ADPD106/ADPD107.

0x0: standby.

0x1: program.

0x2: normal operation.

0x11

[15:14]

0x0

R/W

Reserved

Reserved.

0x0

R/W

RDOUT_MODE

Readback data mode for extended data registers.

0x0: block sum of N samples.

0x1: block average of N samples.

0x1

R/W

FIFO_OVRN_PREVENT

0x0: wrap around FIFO, overwriting old data with new.

0x1: new data if FIFO is not full (recommended setting).

[11:9]

0x0

R/W

Reserved

Reserved.

[8:6]

0x0

R/W

SLOTB_FIFO_MODE

Time Slot B FIFO data format.

0: no data to FIFO.

1: 16-bit sample in digital integration mode or 16-bit sum of all four

channels when not in digital integration mode.

2: 32-bit sample in digital integration mode or 32-bit sum of all four

channels when not in digital integration mode.

3: 16-bit sample and 16-bit background value in digital integration mode.

4: 32-bit sample and 32-bit background value in digital integration

mode or four channels of 16-bit sample data for Time Slot B when not

in digital integration mode.

6: four channels of 32-bit extended sample data for Time Slot B when

not in digital integration mode.

Others: reserved.

The selected Time Slot B data is saved in the FIFO. Available only if Time

Slot A has the same averaging factor, N (Register 0x15, Bits[10:8] =

Bits[6:4]), or if Time Slot A is not saving data to the FIFO (Register 0x11,

Bits[4:2] = 0).

0x0

R/W

SLOTB_EN

Time Slot B enable. 1: enables Time Slot B.

[4:2]

0x0

R/W

SLOTA_FIFO_MODE

Time Slot A FIFO data format.

0: no data to FIFO.

1: 16-bit sample in digital integration mode or 16-bit sum of all

four channels when not in digital integration mode.

2: 32-bit sample in digital integration mode or 32-bit sum of all

four channels when not in digital integration mode.

3: 16-bit sample and 16-bit background value in digital integration mode.

4: 32-bit sample and 32-bit background value in digital integration

mode or four channels of 16-bit sample data for Time Slot B when not

in digital integration mode.

6: four channels of 32-bit extended sample data for Time Slot B when

not in digital integration mode.

Others: reserved.

0x0

R/W

Reserved

Write 0x0.

0x0

R/W

SLOTA_EN

Time Slot A enable. 1: enables Time Slot A.

ADPD107 Datasheet(PDF) 61 Page - Analog Devices

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