ADPD107 datasheet(37/66 Pages) AD

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Data Sheet

ADPD105/ADPD106/ADPD107

Rev. A | Page 37 of 66

fS/2 Output

Setting Register 0x0B, Bits[12:8] or Bits[4:0] = 0x0F configures

the respective pin to provide a signal that toggles at half the

sampling rate. This timing signal is useful in, for example,

situations where more than two LEDs per sample are required.

This signal can be used as a select signal to a multiplexer being

used to mux two LEDs into a single LED driver, providing the

ability to drive up to four separate LEDs per sample period. In

such a case, the ADPD105/ADPD106/ADPD107 are operated at

2× the sampling rate and the LED settings can be reconfigured

during the sleep period between samples. If identical LED settings

(current and timing) are used for the LEDs being muxed, then

up to four LEDs can be sampled per sampling period without

host inter-vention. An example of this configuration is shown in

Figure 43.

The fS/2 timing signal always starts in an active low state when

the device switches from standby mode to normal operating

mode and transitions to a high state at the completion of the

first sample.

Figure 43. Example Using the fS/2 Timing Signal

Logic 0 Output

Setting Register 0x0B, Bits[12:8] or Bits[4:0] = 0x10 configures

the respective pin to provide a Logic 0 output.

Logic 1 Output

Setting Register 0x0B, Bits[12:8] or Bits[4:0] = 0x11 configures

the respective pin to provide a Logic 1 output.

32 kHz Oscillator Output

Setting Register 0x0B, Bits[12:8] or Bits[4:0] = 0x13 configures

the respective pin to provide a copy of the on-board 32 kHz

oscillator.

CALCULATING CURRENT CONSUMPTION

The current consumption of the ADPD105/ADPD106/ADPD107

depends on the user selected operating configuration, as

determined by the following equations.

Total Power Consumption

To calculate the total power consumption, use Equation 4.

Total Power = IVDD_AVG × VDD + ILEDA_AVG × VLEDA +

ILEDB_AVG × VLEDB

(4)

Average VDD Supply Current

To calculate the average VDD supply current, use Equation 5.

IVDD_AVG = DR × ((IAFE_A × tSLOTA) + (IAFE_B × tSLOTB) +

QPROC_X) + IVDD_STANDBY

(5)

where:

DR is the data rate in Hz.

IVDD_STANDBY = 0.2 μA.

QPROC_X is an average charge associated with a processing time,

as follows:

When only Time Slot A is enabled,

QPROC_A (C) = 0.135 × 10−6 + (186 × 10−6 × (2.69 × 10−3 +

(6.2 × 10−3/SCALE_A × ILEDA_PK))

When only Time Slot B is enabled,

QPROC_B (C) = 0.135 × 10−6 + (134 × 10−6 × (2.69 × 10−3 +

(6.2 × 10−3/SCALE_A × ILEDA_PK))

When Time Slot A and Time Slot B are enabled,

QPROC_AB (C) = 0.135 × 10−6 + (206 × 10−6 × (2.69 × 10−3 +

(6.2 × 10−3/SCALE_A × ILEDA_PK))

IAFE_x (A) = 3.0 × 10−3 + (1.5 × 10−3 × NUM_CHANNELS) +

(5.7 × 10−3/SCALE_X × ILEDX_PK)

(6)

tSLOTx (sec) = LEDx_OFFSET + LEDx_PERIOD ×

PULSE_COUNT

(7)

where:

NUM_CHANNELS is the number of active channels.

ILEDX_PK is the peak LED current, expressed in amps, for whichever

LED is enabled in that particular timeslot. Note that in the QPROC

calculations, the processing charge only scales as a function of

the LED current setting for the LED configured to operate in

Time Slot A, regardless of whether or not Time Slot A is enabled.

For this reason, be sure to minimize the LED peak current for

the Time Slot A LED to save power when Time Slot A is not

being used.

SCALE_X is the scale factor for the LED current drive determined

by Bit 13 of the LEDX_DRV registers: Register 0x22, Register 0x23,

and Register 0x24.

LEDx_OFFSET is the pulse start time offset expressed in

seconds.

LEDx_PERIOD is the pulse period expressed in seconds.

PULSE_COUNT is the number of pulses.

ADPD107 Datasheet(PDF) 37 Page - Analog Devices

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