ADPD107 datasheet(43/66 Pages) AD

43 / 66 page

Data Sheet

ADPD105/ADPD106/ADPD107

Rev. A | Page 43 of 66

(dark) portion of the LED response, whereas the positive

sample region falls in the pulsed region of the LED response.

Placing the LED pulse offset, SLOTx_LED_OFFSET, at the

beginning of SLOTx_AFE_OFFSET + 9 + SLOTx_AFE_WIDTH

achieves this timing. The output is the difference of the signals

in the two regions.

Double-sample pair mode is another way to sample. In this

mode, there are two negative sample regions and one long

positive sample region (see Figure 46 and Figure 47). To use

double-sample pair mode, write 0x0 to Register 0x5A, Bit 5 for

Time Slot A, or Bit 6 for Time Slot B. The first negative sample

region starts at SLOTx_AFE_OFFSET + 9 and its duration is set

by SLOTx_AFE_WIDTH. The positive sample region starts at

SLOTx_AFE_OFFSET + 9+ SLOTx_AFE_WIDTH and its

duration is twice the SLOTx_AFE_WIDTH. After this, there is

another negative sample region that starts at SLOTx_AFE_OFFSET

+ 9 + 3 × SLOTx_AFE_WIDTH, and its duration is SLOTx_AFE_

WIDTH. Set the timing such that both of the negative sample

regions fall in the flat (dark) portion of the LED response and

the positive sample region falls in the pulsed portion of the LED

response. Placing the LED pulse offset, SLOTx_LED_OFFSET

at the beginning of SLOTx_AFE_OFFSET + 9 + SLOTx_AFE_

WIDTH achieves this timing. The output is calculated by

summing the response of all the regions in a negative/positive/

negative manner. The double-sample pair mode is useful for cases

when the background light is not constant because it has better

background rejection, but it also uses more power than single-

sample pair mode.

Sample Timing Modes

There are two options for timing the sample regions: gapped

mode and continuous mode.

In gapped timing mode, there is a space between the negative and

positive sample regions. The width of this region is specified by

SLOTA_AFE_FOFFSET for Time Slot A and SLOTB_AFE_

FOFFSET for Time Slot B in 31.25 ns steps. To enable this feature,

write 0x1 to Register 0x5A, Bit 7. This bit enables gapped timing

for the time slot (or time slots) that are in digital integrate mode.

This mode is helpful when there are unwanted transients in the

LED response that must be ignored for an accurate output.

If there are no concerns about LED response transients, select

continuous timing mode. In this mode, there is no space

between the negative and positive sample regions. Write 0x0 to

Both gapped and continuous sample timing modes can be used

with single-sample pair or double-sample pair mode. Example

timing diagrams are shown in Figure 46, Figure 47, Figure 48,

and Figure 49.

Background Values

In digital integrate mode, the digital integration background

value, DI_BACKGROUND, or dark values are also stored and

available as output data. This is in addition to the output value

during the LED pulse, DI_OUTPUT, which has the dark value

subtracted. DI_BACKGROUND is the sum of the negative

region samples.

To include these values in the FIFO, set Register 0x11, Bits[4:2]

for Time Slot A, and Register 0x11, Bits[8:6] for Time Slot B. For

16-bit data, set this value to 0x3; for 32-bit data, set this value to

0x04. These settings are also available through the data registers;

and Register 0x69, Register 0x79, and Register 0x7D for Time

Slot B. It is recommended that the channel offsets (Register 0x18 to

values in the FIFO in digital integration mode. These channel

offsets do not affect the sample values, but do provide more

headroom for the background values.

Saturation Detection in Digital Integrate Mode

In normal operation, when using the band-pass filter and the

integrator, the ADC almost always saturates before the TIA.

Unlike in normal operation, saturation of the TIA or the ADC

cannot be detected solely by looking at the signal value where

the signal value is the positive sample region minus the reference

region in digital integrate mode. This is because the integrated

value does not by itself contain any information indicating

whether one of the ADC conversions during the integration

period exceeded the ADC output range. As a result, the real-

time output may have saturated only for a fraction of the ADC

conversions within a sample and the final accumulated sum may

not reflect this. To detect TIA saturation in digital integration

mode, both the background values, DI_BACKGROUND, and

the signal values, DI_OUTPUT, must be collected. Refer to the

Background Values section for the correct settings for

For single-sample pair mode, saturation has occurred when

(DI_OUTPUT/(min(SLOTx_LED_WIDTH,

SLOTx_AFE_WIDTH)) + DI_BACKGROUND/

AFE_WIDTH)/NUM_PULSES > 0x3FFF

For double-sample pair mode, saturation has occurred when

(DI_OUTPUT/(min(SLOTx_LED_WIDTH, 2 ×

SLOTx_AFE_WIDTH)) + DI_BACKGROUND/(2 ×

SLOTx_AFE_WIDTH))/NUM_PULSES > 0x3FFF

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