ADPD4000 datasheet(18/82 Pages) AD

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ADPD4000/ADPD4001

Data Sheet

Rev. A | Page 18 of 82

state. The entire decimation path uses a 32-bit datapath. It is up

to the user to ensure that there is no undesired overflow.

Final data results can be read from data registers or a 256-byte

data FIFO. Data written to the FIFO is configurable to allow the

different data registers, formats, and data sizes as required. All

time slots that write data to the FIFO must use the same output

data rate by using the same decimation rate. Data from time slots

operating at different output data rates than that which is being

written to the FIFO must be read from the corresponding data

At the end of each time slot or decimation period, the selected

data is written to the FIFO as a packet. This packet can include

0, 8-, 16-, 24-, or 32-bit data for each of the dark data and signal

data values. The bit alignment of the data written to the FIFO is

selectable with a shift of 0 bits to 31 bits, with saturation

provided. Lower bits are ignored. The DARK_SHIFT_x and

SIGNAL_SHIFT_x bit fields select the number of bits to shift

the output data to the right before writing to the FIFO. The

DARK_SIZE_x and SIGNAL_SIZE_x bit fields select the number

of bytes of each field to be written from 0 bytes to 4 bytes. When

set to 0, no data is written for that data type. If there are any

nonzero bits at more significant bit positions than those

selected, the data written to the FIFO is saturated. If both

channels are enabled, all selected Channel 1 data values are

written to the FIFO first, followed by the Channel 2 data.

For example, in modes that utilize dark data, the eight upper

bits of the dark data can be stored with 24 appropriately selected

bits from the signal data for each time slot to allow detection of

whether the ambient light is becoming large, while limiting the

size of the amount of data transferred.

The FIFO is never written with partial packets of data. This

means that if there is not enough room for all of the data that is

to be written to the FIFO for all enabled time slots and any

selected status bytes, no data is written from any of the time

slots during that period and the INT_FIFO_OFLOW status bit

is set.

ADC

(14 BITS UNSIGNED)

CHx_ADC_ADJUST

POSITIVE ACCUMULATION

32 BITS SIGNED

NEGATIVE ACCUMULATION

32 BITS SIGNED

ACCORDING TO

SUBTRACT OR DIGITAL

INTEGRATION REGION

15 BITS SIGNED

SIGNAL

DARK

SIGNAL DATA

32 BITS UNSIGNED

DARK DATA

32 BITS UNSIGNED

CLIP

PER CHANNEL

AND PER TIMESLOT

DECIMATION

DATA REGISTERS

ADD 2048 IF

ZERO_ADJUST_x = 1

–

Figure 21. Datapath Block Diagram

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