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Data Sheet

ADPD4000/ADPD4001

Rev. A | Page 23 of 82

Interrupt Outputs, Interrupt X and Interrupt Y

The ADPD4000/ADPD4001 support two separate interrupt

outputs, Interrupt X and Interrupt Y. Each interrupt has the option

to be driven to any of the four GPIO pins. The two different

interrupt outputs can be generated for a host processor if desired.

For example, the FIFO threshold interrupt, INT_FIFO_TH, can

be routed to Interrupt X and used to drive the direct memory

access (DMA) channel of the host, while the INT_FIFO_

OFLOW and INT_FIFO_UFLOW interrupts can be routed to

Interrupt Y and used to drive an additional host interrupt pin.

Another example case includes routing the data interrupt from

a single time slot to Interrupt X and the FIFO threshold

interrupt to Interrupt Y. The host receives one interrupt when

the interrupt of that particular channel occurs and the host can

then read that register directly. Interrupt Y, in this case, is

handled by the host with DMA or with an interrupt. Each of the

different interrupt status bits can be routed to Interrupt X or

Interrupt Y, or both.

For each interrupt, there is an associated Interrupt X and

Interrupt Y enable bit. See Table 27 for a full list of available

interrupts that can be brought out on Interrupt X and Interrupt Y.

The logic for the Interrupt X and Interrupt Y function is a logic

AND of the status bit with its matching enable bit. All enabled

status bits are then logically OR’ed to create the interrupt

function. The enable bits do not affect the status bits.

General-Purpose I/Os

The ADPD4000/ADPD4001 provide four general-purpose I/O

pins: GPIO0, GPIO1, GPIO2, and GPIO3. These GPIOs can be

used as previously described in the Interrupt Outputs, Interrupt

X and Interrupt Y section for interrupt outputs or for providing

external clock signals to the device. The GPIOs can also be used

for many different control signals, as synchronization controls

to external devices, as well as test signals that are useful during

system debugging. All of the available signals that can be

brought out on a GPIOx pin are listed in Table 31.

SPI and I2C Interface

The ADPD4000 contains a SPI port, the ADPD4001 contains

an I2C interface. The SPI and I2C interfaces operate synchro-

nously with their respective input clocks and require no internal

clocks to operate.

The ADPD4000/ADPD4001 have an internal power-on-reset

circuit that sets the device into a known idle state during the

initial power-up. After the power-on-reset has been released,

approximately 2 µs to 6 μs after the DVDD supply is active, the

device can be read and written through the SPI or I2C interface.

The registers are accessed using addresses within a 15-bit

address space. Each address references a 15-bit register with one

address reserved for the FIFO read accesses. For both the I2C

and SPI interfaces, reads and writes auto-increment to the next

access sequence. This automatic address increment occurs for

all addresses except the FIFO address, one less than the FIFO

address and the last used address, which is 0x277. Reads from

the FIFO address continue to access the next byte from the FIFO.

SPI Operations

The SPI single register write operation is shown in Figure 24.

The first two bytes contain the 15-bit register address and specifies

that a write is requested. The remaining two bytes are the 16

data bits to write to the register. The register write occurs only

when all 16 bits are shifted in prior to deassertion of the CS signal.

In addition, multiple registers can be written if additional 16-bit

data is shifted in before deassertion of the CS signal. The

after each 16 bits of data.

The SPI single register read operation is shown in Figure 25.

The first two bytes contain the 15-bit register address and

specifies that a read is requested. Register bits are shifted out

starting with the MSB. In addition, multiple registers can be

read if additional 16-bit data is shifted out prior to deassertion

of the CS signal.

It is recommended that reading from the FIFO is done byte

wise. There is no requirement to read multiples of 16 bits.

I2C Operations

The I2C operations require addressing the device as well as

choosing the register that is being read or written. An I2C

is bidirectional open drain, where different bit times are driven

in a predetermined way by the master or the slave. The ADPD4001

acts as a slave on the I2C bus. Start and stop bit operations are

shown as S and P in Figure 26 and Figure 27. The I2C port

supports both 7-bit and 15-bit addresses. If accessing Address

0x007F or lower, a 7-bit address can be used. If the first address

bit after the slave address acknowledge (ACK) is a 0, a 7-bit

address is used, as shown in the short read and write operations

(see Figure 26 to Figure 29). If the first bit after a slave address

acknowledge is 1, a 15-bit address is used as shown in the long

read and write operations (see Figure 30 and Figure 31).

Figure 26 shows the first half of the short register write operation.

The first byte indicates that the ADPD4001 is being addressed

with a write operation. The ADPD4001 indicates that it has

been addressed by driving an acknowledge. The next byte

operation is a write of the address of the register to be written.

The MSB is the L/S bit (long/short). When this bit is low, a 7-bit

address follows. If the L/S bit is high, a 15-bit address follows.

The ADPD4001 sends an acknowledge following the register

address.

The rest of the write operation is shown in Figure 27, which

shows the two data bytes that are written to the 16-bit register.

Registers are written only when all 16 bits are shifted in before a

stop bit occurs. The ADPD4001 sends an acknowledge for each

byte received. Additional pairs of byte operations can be repeated

prior to the stop bit occurring. The address auto-increments

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