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ADPD4000/ADPD4001

Data Sheet

Rev. A | Page 20 of 82

The setup for using the time stamp operation is as follows:

1. Configure a GPIO to support the time stamp input using

the appropriate GPIO_PIN_CFGx bit field. Select the

matching GPIO to provide the time stamp using the

TIMESTAMP_GPIO bit field.

2. Configure the ADPD4000/ADPD4001 for operation and

enable the low frequency oscillator.

3. If the TIMESTAMP_SLOT_DELTA function is desired,

start time slot operation by placing the device in go mode

using the OP_MODE bit (see Table 15). For low frequency

oscillator calibration, it is only required that the low

frequency oscillator be enabled. The device does not have

to be in go mode for low frequency oscillator calibration.

Use the following procedure to capture the time stamp:

1. Set the CAPTURE_TIMESTAMP register bit to 1 to enable

capture of the time stamp on the next rising edge on the

selected GPIO input.

2. The host provides the initial time stamp trigger on the

selected GPIO at an appropriate time.

3. The CAPTURE_TIMESTAMP bit is cleared when the

time stamp signal is captured unless the TIMESTAMP_

ALWAYS_EN bit is set, in which case, the capture of the

time stamp is always enabled. Reenable the capture if

necessary.

4. The host provides a subsequent time stamp trigger on the

selected GPIO at an appropriate time.

5. The number of low frequency oscillator cycles that

occurred between time stamp triggers can now be read

from the TIMESTAMP_COUNT_x bit fields.

The host must continue to handle the FIFO and/or data register

data normally during time stamp processing.

If using a dedicated pin for a time stamp that does not have

transitions other than the time stamp, set the TIMESTAMP_

ALWAYS_EN bit to avoid automatic clearing of the CAPTURE_

TIMESTAMP bit. This setting removes the need to enable the

time stamp capture each time.

The time stamp can calibrate the low frequency oscillator as

described in the Low Frequency Oscillator Calibration section.

The host can also use TIMESTAMP_ SLOT_DELTA to determine

when the next time slot occurs. TIMESTAMP_SLOT_DELTA

can be used to determine the arrival time of the samples currently

in the FIFO. TIMESTAMP_SLOT_DELTA does not account for

the decimation factor.

The time stamp trigger is edge sensitive and can be set to either

trigger on the rising edge (default) or falling edge using

TIMESTAMP_INV.

LOW FREQUENCY OSCILLATOR CALIBRATION

The time stamp circuitry can be used to calibrate either the

32 kHz or 1 MHz low frequency oscillator circuit by adjusting

the frequency to match the timing of the time stamp triggers.

Simply compare the TIMESTAMP_COUNT_x value in low

frequency oscillator cycles to the actual time stamp trigger

period and adjust the OSC_32K_ADJUST or OSC_1M_FREQ_

ADJ value accordingly.

HIGH FREQUENCY OSCILLATOR CALIBRATION

The high frequency oscillator is calibrated by comparing

multiples of its cycles with multiple cycles of the low frequency

oscillator, which is calibrated to the system time. Calibration of

the low frequency oscillator precedes calibration of the high

frequency oscillator. The method for calibrating the high

frequency oscillator is as follows:

1. Write 1 to the OSC_32M_CAL_START bit.

2. The ADPD4000/ADPD4001 automatically power up the

high frequency oscillator.

3. The device automatically waits for the high frequency

oscillator to be stable.

4. An internal counter automatically counts the number of

32 MHz high frequency oscillations that occur during

128 cycles of the 1 MHz low frequency oscillator or

32 cycles of the 32 kHz low frequency oscillator, depending

on which low frequency oscillator is enabled based on the

setting of LFOSC_SEL.

5. The OSC_32M_CAL_COUNT bit field is updated with the

final count.

6. The 32 MHz oscillator automatically powers down

following calibration unless time slots are active.

7. The device resets the OSC_32M_CAL_START bit

indicating the count has been updated.

The OSC32M_FREQ_ADJ bit field adjusts the frequency of the

32 MHz oscillator to the desired frequency. When using an external

low frequency oscillator, the 32 MHz oscillator calibration is per-

formed with respect to the externally provided low frequency

oscillator.

TIME SLOT OPERATION

Operation of the ADPD4000/ADPD4001 is controlled by an

internal configurable controller that generates all the timing

needed to generate sampling regions and sleep periods.

Measurements of multiple sensors and control of synchronous

stimulus sources is handled by multiple time slots. The device

provides up to 12 time slots for multisensor applications. The

enabled time slots are repeated at the sampling rate, which is

configured by the 23-bit TIMESLOT_PERIOD_x bit field in the

TS_FREQ register. The sampling rate is determined by the

following formula:

Sampling Rate = Low Frequency Oscillator Frequency (Hz) ÷

TIMESLOT_PERIOD_x

Each time slot allows the creation of one or more LED and/or

modulation pulses, and the acquisition of the photodiode or

other sensor current based on that stimulus. The operating

parameters for each time slot is highly configurable.

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