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ADF7030 Datasheet(PDF) 8 Page - Analog Devices

Part # ADF7030
Description  High Performance, Low Power, 169 MHz ISM Band, Radio Transceiver IC
PDF  24 Pages
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Manufacturer  AD [Analog Devices]
Direct Link  http://www.analog.com
Logo AD - Analog Devices

ADF7030 Datasheet(HTML) 8 Page - Analog Devices

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ADF7030
Data Sheet
DIGITAL TIMING SPECIFICATIONS
VDD = VBAT1 = VBAT2 = VBAT3 = VBAT4 = VBAT5 = VBAT6 = 2.2 V to 3.6 V. EPAD = 0 V (ground), TA = TMIN to TMAX, unless
otherwise noted.
Table 6. SPI Interface Timing
Parameter
Description
Min
Typ
Max
Unit
t1
Falling edge to MISO setup time
15
ns
t2
CS low to SCLK setup time
40
ns
t3
SCLK high time
40
ns
t4
SCLK low time
40
ns
t5
SCLK period
80
ns
t6
SCLK falling edge to MISO delay
10
ns
t7
MOSI to SCLK rising edge setup time
5
ns
t8
MOSI to SCLK rising edge hold time
5
ns
t9
SCLK falling edge to CS hold time
40
ns
t10
CS high time
80
ns
t11
CS low to MISO high wake-up time
92
µs
t12
MISO high to SCLK setup time
SCLK low time
µs
Timing Diagrams
t4
t3
t2
t1
t6
t7
t8
t5
t9
t10
SCLK
MISO
MOSI
7
7
6
5
4
3
2
1
0
7
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
BIT 7
BIT 0
X
BIT 7
CS
Figure 2. SPI Interface Timing
SPI STATE
SCLK
MISO
SLEEP
WAKE UP
SPI READY
X
0
1
2
3
4
5
6
7
t11
t12
t9
t6
CS
Figure 3. PHY_SLEEP to SPI Ready State Timing
Rev. 0 | Page 8 of 24



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