Data Sheet

ADF7030

Pin No.

Mnemonic

Description

29

GPIO6

Digital GPIO Pin 6

30

DNC

Do Not Connect. Do not connect to this pin.

31

DNC

Do Not Connect. Do not connect to this pin.

32

GPIO7

Digital GPIO Pin 7.

33

DNC

Do Not Connect. Do not connect to this pin.

34

CREG5

Regulator Output 5. Place a 220 nF capacitor between this pin and ground for regulator stability and noise rejection.

35

HFXTALP

Do Not Connect. Do not connect to this pin.

36

HFXTALN

Reference Input. Connect this pin to an external 26 MHz reference (typically a TCXO).

37

CREG6

Regulator Output 6. Place a 220 nF capacitor between this pin and ground for regulator stability and noise rejection.

38

CREG7

Regulator Output 7. Place a 220 nF capacitor between this pin and ground for regulator stability and noise rejection.

39

CLF

External Loop Filter Capacitor to CREG1. Place a 1.2 nF capacitor between this pin and the CREG1 pin.

40

VBAT6

Power Supply Pin 6 to the Internal Regulators.

EPAD

Exposed Pad. Connect the exposed pad to ground.

Rev. 0 | Page 11 of 24