IMXRT500EC datasheet(39/119 Pages) NXP

Part #	IMXRT500EC

Description	i.MX RT500 Low-Power Crossover Processor Data Sheet with Addendum

PDF	119 Pages

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Manufacturer	NXP [NXP Semiconductors]

Direct Link	http://www.nxp.com

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39 / 119 page

T CLK

tV(Q)min

fclk

V(Q)max

IO[0:7]

V(Q)max

Figure 18. DDR mode (output timing, mode 0 and 1)

TCLK

t V(Q)max

tV(Q)min

tV(Q)max

IO[0:7]

DQS

V(Q)min

Figure 19. DDR mode (output timing, mode 3)

1.5 Display and graphics

1.5.1 LCDIF

Tamb = -20 °C to 70 °C; VDD = 2.7 V to 3.6 V; CL = 30 pF. Simulated values.

Table 27. LCDIF characteristics

Symbol

Parameter

Conditions

Min.

Typ.

Max.

Unit

fclk

clock frequency

on pin LCD_DCLK

MHz

tv(Q)

data output valid time

on all LCD output pins

0.3

4.5

1.5.2 MIPI DSI timing

The i.MX RT500 conforms to the MIPI D-PHY electrical specifications MIPI DSI

Version 1.01 and D-PHY specification Rev. 1.0 (and also DPI version 2.0, DBI version

2.0, DSC version 1.0a at protocol layer) for MIPI display port x2 lanes.

External memory interface

i.MX RT500 Low-Power Crossover Processor, Rev. 0, 02/2021

NXP Semiconductors

IMXRT500EC Datasheet(PDF) 39 Page - NXP Semiconductors

IMXRT500EC Datasheet(HTML) 39 Page - NXP Semiconductors

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