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IMXRT500EC Datasheet(PDF) 60 Page - NXP Semiconductors |
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IMXRT500EC Datasheet(HTML) 60 Page - NXP Semiconductors |
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60 / 119 page  Table 44. MIPI-I3C specifications when communicating with legacy I2C devices (continued) Symbol Characteristic 400 kHz/Fast mode 1 MHz/ Fast+ mode Unit Min. Max. Min. Max. START condition tLOW LOW period of the SCL clock 1300 — 500 — ns tHIGH HIGH period of the SCL clock 600 — 260 — ns tSU_DAT Data set-up time 100 — 50 — ns tHD_DAT Data hold time for I2C bus devices — — — — ns tf Fall time of SDA and SCL signals 20*(Vdd/5.5 v) 300 20*(Vdd/5. 5 v) 120 ns tr Rise time of SDA and SCL signals 20 300 — 120 ns tSU_STO Set-up time for STOP condition 600 — 260 — ns tBUF Bus free time between STOP and START condition 1.3 — 0.5 — µs tSP Pulse width of spikes that must be suppressed by the input filter 0 50 0 50 ns Table 45. MIPI-I3C open drain mode specifications Symbol Characteristic Min. Max. Unit Notes tLOW_OD LOW period of the SCL clock 200 — ns tDIG_OD_L tLOW_OD + tfDA_OD (min) — ns tHIGH HIGH period of the SCL clock — 41 ns tfDA_OD Fall time of SDA signal tCF 12 ns 1 tSU_OD Data set-up time during open drain mode 3 — ns tCAS Clock after START (S) Condition • ENTAS0 • ENTAS1 • ENTAS2 • ENTAS3 38.4 n 1 μ 100 μ 2 m 50 m s s s s tCBP Clock before STOP (P) condition tCAS(min)/2 — ns tMMOverlap Current master to secondary master overlap time during handoff tDIG_OD_L — ns tAVAL Bus available condition 1 — μs tIDLE Bus idle condition 1 — ms tMMLock Time internal where new master not driving SDA low tAVAL — μs 1. Cb = total capacitance of the one bus line in pF. External memory interface i.MX RT500 Low-Power Crossover Processor, Rev. 0, 02/2021 59 NXP Semiconductors |
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