IMXRT500EC datasheet(49/119 Pages) NXP

49 / 119 page

1.7.3 I2S-bus interface

Tamb = -20 °C to 70 °C; VDD = 1.71 V to 1.89 V; CL = 30 pF balanced loading on all pins; Input slew = 1.0 ns, SLEW setting =

standard mode for all pins; Parameters sampled at the 50 % level of the rising or falling edge.

Table 35. I2S-bus interface pins1, 2

Symbol

Parameter

Conditions

Notes

Min.

Typ.3

Max.

Unit

Common to master and slave

tWH

pulse width

HIGH

on pins I2Sx_TX_SCK and I2Sx_RX_SCK4

(Tcyc/2) -1

(Tcyc/2) +1

tWL

pulse width

LOW

on pins I2Sx_TX_SCK and I2Sx_RX_SCK4

(Tcyc/2) -1

(Tcyc/2) +1

Master

tv(Q)

data output

valid time

on pin

I2Sx_TX_SD

6.798

17.505

on pin I2Sx_WS

16.055

tsu(D)

data input set-

up time

on pin

I2Sx_RX_SD

1.3

th(D)

data input

hold time

on pin

I2Sx_RX_SD

2.9

Slave

tv(Q)

data output

valid time

on pin

I2Sx_TX_SD

13.8

23.6

tsu(D)

data input set-

up time

on pin

I2Sx_RX_SD

4.7

on pin

I2Sx_WS

0.9

th(D)

data input

hold time

on pin

I2Sx_RX_SD

on pin

I2Sx_WS

1. Based on simulation; not tested in production.

2. The Flexcomm Interface function clock frequency should not be above 48 MHz. See the data rates section in the I2S

chapter in the i.MX RT500 Low-Power Crossover MCU Reference Manual (IMXRT500RM) to calculate clock and sample

rates.

3. Typical ratings are not guaranteed.

4. Based on simulation. Not tested in production.

5. Clock Divider register (DIV) = 0x0.

External memory interface

i.MX RT500 Low-Power Crossover Processor, Rev. 0, 02/2021

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