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IMXRT500EC Datasheet(PDF) 74 Page - NXP Semiconductors |
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IMXRT500EC Datasheet(HTML) 74 Page - NXP Semiconductors |
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74 / 119 page ![]() M33 active, running enhanced-while(1) code in different partitions. Typical silicon, VDDCore=1.1V, Temperature=25 ℃, FBB, HCLK=192MHz (FRO). All memories array/periphery ON (PDRUNCFG2/3) and only one partition clocked (AHB_SRAM_ACCESS_DISABLE register). Figure 35. Current consumption vs. memory partitions 3.2 Standard I/O pin configuration The following figure shows the possible pin modes for standard I/O pins: The default configuration for standard I/O pins is Z mode. The weak MOS devices provide a drive capability equivalent to pull-up and pull-down resistors. Application information i.MX RT500 Low-Power Crossover Processor, Rev. 0, 02/2021 73 NXP Semiconductors |
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