IMXRT500EC datasheet(4/119 Pages) NXP

4 / 119 page

Graphics/Multimedia

• 2D Vector Graphics Processing Unit, running at

frequencies of up to 200 MHz.

• LCD Display Interface supporting smart LCD displays

and video mode.

• MIPI DSI Interface with on-chip PHY supporting

transfer rates up to 895.1 Mbps.

• FlexIO can be configured to provide a parallel interface

to an LCD

I/O Peripherals

• Up to 136 general purpose I/O (GPIO) pins with

configurable pull-up/pull-down resistors. Ports can be

written as words, half-words, bytes, or bits.

• Mirrored, secure GPIO0.

• Individual GPIO pins can be used as edge and level

sensitive interrupt sources, each with its own interrupt

vector.

• All GPIO pins can contribute to one of two ganged

(OR’d) interrupts from the GPIO_HS module.

• A group of up to 7 GPIO pins (from Port0/1) can be

selected for Boolean pattern matching which can

generate interrupts and/or drive a “pattern-match”

output.

• Adjustable output driver slew rates.

• JTAG boundary scan

Security

•

Secure Isolation: Protection from software and remote

attacks using Trustzone for armV8M. Hardware

isolation of AES keys

•

Secure Boot: firmware in ROM providing immutable

root of trust

•

Secure Storage: Physically Unclonable Function

(PUF) based key store, On-the-fly-AES decryption

(OTFAD) of off-chip flash for code storage

•

Secure Debug: Certificate based debug authentication

mechanism

•

Secure Loader: Supports firmware update mechanism

with authenticity (RSA signed) and confidentiality

(AES-CTR encrypted) protection

•

Secure Identity: 128-bit Universal Unique Identifier

(UUID), 256-bit Compound Device Identifier (CDI) per

TCG DICE specification

• Cryptographic Accelerators

• Symmetric cryptography (AES) with

128/192/256-bit key strength and protection

against Side-channel analysis (Differential Power

Analysis and Template attacks)

• Asymmetric cryptography acceleration using

CASPER co-processor

• NIST SP 800-90b compliant TRNG design with

512-bit output per call

• Hash engine with SHA-256 and SHA1

May be run from the FRO, the crystal

oscillator or the CLKIN pin.

• a second, independent PLL output provides

alternate high-frequency clock source for the

DSP CPU if the required frequency is different

from the main system clock. (Note: 2nd PFD

output from Main System PLL)

• two additional PLL outputs provide potential

clock sources to various peripherals.

• Audio PLL for the audio subsystem.

Power Control

• Main external power supply: 1.8V ± 5%

• Vddcore supply (from PMIC or internal PMU):

adjustable from 0.6 V to 1.1 V (including retention

mode)

• Analog supply: 1.71-3.6 V

• Five VDDIO supplies (can be shared or

independent): 1.71 - 3.6 V

• USB Supply: 3.0-3.6 V

• Reduced power modes:

• Sleep mode: CPU clock shut down (each CPU

independently)

• Deep_sleep mode: User-selectable

configuration via PDSLEEPCFG

• Deep_powerdown mode: Internal power

removed from entire chip except “always-on”

domain

• Each individual SRAM partition can be

independently powered-off or put into a low-

power retain mode

• DSP Domain can be powered-off

independently from the rest of the system.

• Ability to operate the synchronous serial

interfaces in sleep or deep-sleep as a slave or

USART clocked by the 32 kHz RTC oscillator

• Wake-up from low-power modes via interrupts

from various peripherals including the RTC

and the OS/Event timer

• RBB/FBB to provide additional control over power/

performance trade-offs

• Power-On Reset (POR).

Operating characteristics

• Temperature range (ambient): -20 °C to +70 °C

• VDDCORE: 0.7 V - 1.155 V

• VDDIO_0/1/2/4: 1.71 V - 1.89 V

• VDDIO_3: 1.71 V - 3.6 V

i.MX RT500 Low-Power Crossover Processor, Rev. 0, 02/2021

NXP Semiconductors

IMXRT500EC Datasheet(PDF) 4 Page - NXP Semiconductors

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