MCP33131 datasheet(35/54 Pages) MICROCHIP

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 2018 Microchip Technology Inc.

DS20006122A-page 35

MCP33131/MCP33121/MCP33111-XX

6.4.3

SAMPLE (THROUGHPUT) RATE

The device completes data conversion within the

maximum specification of the data conversion time

(tCNV). The continuous input sample rate is the inverse

of the sum of input acquisition time (tACQ) and data

conversion time (tCNV). Equation 6-8 shows the

continuous sample rate calculation using the minimum

and maximum specifications of the input acquisition

time (tACQ) and data conversion time (tCNV).

EQUATION 6-8:

SAMPLE RATE

6.4.4

SERIAL SPI CLOCK FREQUENCY

REQUIREMENT

The ADC output is collected during the input acquisition

time (tACQ). For continuous input sampling and data

conversion sequence, the SPI clock frequency should

be fast enough to clock out all output data bits during

the input acquisition time (tACQ). For the continuous

sampling rate (fS), the minimum SPI clock frequency

requirement is determined by the following equation:

EQUATION 6-9:

SPI CLOCK FREQUENCY

REQUIREMENT

where fSCLK is the minimum SPI serial clock frequency

required to transfer all N-bits of output data during input

acquisition time (tACQ).

Table 6-4 and Table 6-5 show the examples of calcu-

lated minimum SPI clock (fSCLK) requirements for vari-

ous input acquisition times for 1 Msps and 500 kSPS

family devices, respectively.

tACQ tCNV



----------------------------------

Sample Rate =

290ns 710ns



-----------------------------------------1 Msps

(a) MCP331x1-10:

Sample Rate =

700ns 1300ns



--------------------------------------------500 kSPS

(b) MCP331x1-05:

Sample Rate =

where N is the number of output data bits, given by

fSCLK

TSCLK

---------------

tACQ

tQUIET tEN



–

------------------------------------------------------

tACQ

NTSCLK



tQUIET tEN

N= 16-bit for MCP33131-XX

= 14-bit for MCP33121-XX

= 12-bit for MCP33111-XX

TSCLK = Period of SPI clock

N x TSCLK = Output data window

tQUIET = Quiet time between the last output bit

and beginning of the next

conversion start.

= 10 ns (min)

tEN = Output enable time = 10 ns (max), with

DVIO ≥2.3V

Note:

See Figure 1-1 for digital interface timing dia-

gram.

TABLE 6-4:

SPI CLOCK SPEED VS. INPUT ACQUISITION TIME (TACQ) FOR MCP331X1-10

Input

Acquisition Time:

tACQ (nS)

(Note 4)

Data

Conversion Time:

tCNV (nS)

(Note 5)

SPI Clock (fSCLK) Speed Requirement

(Note 1), (Note 2)

Sample Rate:

fS (Msps)

Conditions

MCP33131-10

(16-bit)

MCP33121-10

(14-bit)

MCP33111-10

(12-bit)

250

750

69.57 MHz

60.87 MHz

52.17 MHz

85°C < TA ≤ 125°C

(Note 3)

270

64 MHz

56 MHz

48 MHz

0.98

280

61.54 MHz

53.85 MHz

46.15 MHz

0.97

290

710

59.26 MHz

51.85 MHz

44.44 MHz

-40°C ≤ TA ≤ 85°C

300

57.15 MHz

50 MHz

42.86 MHz

0.99

320

53.33 MHz

46.67 MHz

40 MHz

0.97

400

42.11 MHz

36.84 MHz

30 MHz

0.9

540

30.77 MHz

26.92 MHz

23.08 MHz

0.8

720

22.86 MHz

20 MHz

17.14 MHz

0.7

720

17.2 MHz

15.05 MHz

12.9 MHz

0.6

1290

12.6 MHz

11.02 MHz

9.45 MHz

0.5

1750

9.04 MHz

7.91 MHz

6.78 MHz

0.4

2620

6.15 MHz

5.39 MHz

4.62 MHz

0.3

4290

3.75 MHz

3.28 MHz

2.81 MHz

0.2

9290

1.73 MHz

1.51 MHz

1.3 MHz

0.1

Note

This is the minimum SPI clock speed requirement to collect all N-bits of the ADC output during the input acquisition time (tACQ), when the

ADC is operating in continuous input sampling mode.

See Equation 6-9 for the calculation of the SPI clock speed requirement.

In extended temperature range, the device takes longer data conversion time (tCNV: 750 nS, max). Using a shorter input acquisition time

is recommended (tACQ: 250 nS) for 1 Msps throughput rate.

Input acquisition time (tACQ) is user-controllable.

Data conversion time (tCNV) is not user-controllable.

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