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MCP33131 Datasheet(PDF) 38 Page - Microchip Technology

Part # MCP33131
Description  1 Msps/500 kSPS 16/14/12-Bit Single-Ended Input SAR ADC
PDF  54 Pages
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Manufacturer  MICROCHIP [Microchip Technology]
Direct Link  http://www.microchip.com
Logo MICROCHIP - Microchip Technology

MCP33131 Datasheet(HTML) 38 Page - Microchip Technology

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DS20006122A-page 38
 2018 Microchip Technology Inc.
MCP33131/MCP33121/MCP33111-XX
7.0
DIGITAL SERIAL INTERFACE
The device has a SPI-compatible serial digital
interface using four digital pins: CNVST, SDI, SDO and
SCLK.
Figure 7-1 shows the connection diagram with the host
device and Figure 7-2 shows the SPI-compatible serial
interface timing diagram.
The SDI pin can be tied to the digital I/O interface
supply voltage (DVIO) or just maintain logic “High” level
by the host. The CNVST pin is used for both chip select
(CS) and conversion-start control.
A rising edge on CNVST initiates the conversion
process. Once the conversion is initiated, the device
will complete the conversion regardless of the state of
CNVST. This means the CNVST pin can be used for
other purposes during tCNV.
When the conversion is complete, the output is
available at SDO by lowering CNVST. Data is sent
MSB-first and changes on the falling edge of SCLK.
Output data can be sampled on either edge of SCLK.
However, a digital host capturing data on the falling
edge of SCLK can achieve a faster read out rate.
SDO returns to high-Z state after the last data bit is
clocked out or when CNVST goes high, whichever
occurs first.
FIGURE 7-1:
Digital Interface Connection
Diagram.
FIGURE 7-2:
SPI Compatible Serial Interface Timing Diagram (16-bit device).
CNVST
SCLK
SDO
CS
SCLK
SDI
(a) MCP33131/21/11-XX
(b) Host Device (Master)
Note 1: Adding this pull-up is needed when monitoring
status of Recalibrate.
DVIO
(Note 1)
10 k
SDI
DVIO
CNVST
SDO
SCLK
1
2
3
14
15
16
4
D15
D14
D13
D12
D2
D1
D0
ADC State
(MSB)
Hi-Z
Hi-Z
tCNVH
tCNV (MAX)
tSCLK
tSCLK_L tSCLK_H
tDO
tDIS
Conversion
(a) Exit input acquisition mode and
(b) Enter new conversion mode
Note 1: SDI must maintain “High” during the entire
tCYC.
(Note 2)
Input Acquisition
Input Acquisition
(tCNV)
(tACQ)
(tACQ)
tCYC
2: Any SCLK toggling events (dummy clocks) before CNVST is changed to “Low” are ignored.
SDI = DVIO
tSU_SDIH_CNV
(Note 1)
tEN
tQUIET
tEN
(Note 3)
(Note 4)
3: tEN when CNVST is lowered after tCNV (Max).
4: tEN when CNVST is lowered before tCNV (Max).
= 1/fS
(Note 5)
5: Recommended data detection: Detect SDO on the falling edge of SCLK.



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