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TEST PATTERNS

(1)

ADS5242

SBAS330C – OCTOBER 2004 – REVISED OCTOBER 2005

SERIAL INTERFACE REGISTERS

ADDRESS

DATA

DESCRIPTION

REMARKS

D7

D6

D5

D4

D3

D2

D1

D0

0

0

0

0

LVDS BUFFERS (Register 0)

All Data Outputs

0

0

Normal ADC Output

(default after reset)

0

1

Deskew Pattern

1

0

Sync Pattern

See Test Patterns

1

1

Custom Pattern

0

0

Output Current in LVDS = 3.5mA

(default after reset)

0

1

Output Current in LVDS = 2.5mA

1

0

Output Current in LVDS = 4.5mA

1

1

Output Current in LVDS = 6.0mA

0

0

0

1

CLOCK CURRENT (Register 1)

0

X

X

0

Default LVDS Clock Output Current

0

X

X

1

0

0

0

1

LSB/MSB MODE (Register 1)

0

0

X

X

LSB First Mode

(default after reset)

0

1

X

X

MSB First Mode

0

0

1

0

POWER-DOWN ADC CHANNELS

(Register 2)

0

1

0

X

D2: Power-Down for Channel 2

Logic 1 = Channel Powered

Down

0

X

0

1

D0: Power-Down for Channel 1

0

0

1

1

POWER-DOWN ADC CHANNELS

(Register 3)

1

0

X

0

D3: Power-Down for Channel 4

Logic 1 = Channel Powered

Down

X

0

1

0

D1: Power-Down for Channel 3

CUSTOM PATTERN (Registers 4–6)

D3

D2

D1

D0

Bits for Custom Pattern

See Test Patterns

0

1

0

0

X

X

X

X

0

1

0

1

X

X

X

X

0

1

1

0

X

X

X

X

(1)

programmed in register 0. The current drive of the data buffers remains the same as the setting in register 0.

LSB

MSB

D0

D1

D2

D3

D4

D5

D6

D7

D8

D9

D10

D11

Deskew Pattern

1

0

1

0

1

0

1

0

1

0

1

0

Sync Pattern

0

0

0

0

0

0

1

1

1

1

1

1

D0(4)

D1(4)

D2(4)

D3(4)

D0(5)

D1(5)

D2(5)

D3(5)

D0(6)

D1(6)

D2(6)

D3(6)

(1)

This table indicates the LSB and MSB of the various patterns. LSB first mode means that the LSB comes out as the first bit of the word.

In the MSB first mode, the MSB comes out as the first bit of the word. The first bit of the word is the one that comes soon after the rising

(2)

The serial output stream comes out LSB first by default.

(3)

D11...D0 represent the 12 output bits from the ADC.

(4)

D0(4) represents the content of bit D0 of register 4, D3(6) represents the content of bit D3 of register 6, etc.

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