ADS5242IPAP datasheet(20/29 Pages) TI

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OVERVIEW

DRIVING THE ANALOG INPUTS

CM Buffer

Internal

Voltage

Reference

Input

Circuitry

IN+

−

600

Ω

600

Ω

ADS5242

NOTE: Dashed area denotes one of four channels.

ADS5242

SBAS330C – OCTOBER 2004 – REVISED OCTOBER 2005

data externally has multiple advantages, such as a

reduced number of output pins (saving routing space

THEORY OF OPERATION

on the board), reduced power consumption, and

reduced effects of digital noise coupling to the analog

circuit inside the ADS5242.

The ADS5242 is a 4-channel, high-speed, CMOS

The ADS5242 operates from two sets of supplies and

ADC.

consists

high-performance

grounds. The analog supply/ground set is denoted as

sample-and-hold circuit at the input, followed by a

AVDD/AVSS, while the digital set is denoted by

12-bit ADC. The 12 bits given out by each channel

LVDD/LVSS.

are serialized and sent out on a single pair of pins in

LVDS format. All four channels of the ADS5242

operate from a single clock referred to as ADCLK.

The sampling clocks for each of the four channels are

The analog input biasing is shown in Figure 35. The

generated from the input clock using a carefully

inputs are biased internally using two 600

Ω resistors

matched clock buffer tree. The 12x clock required for

to enable AC-coupling. A resistor greater than 20

Ω is

the serializer is generated internally from ADCLK

recommended in series with each input pin.

using a phase lock loop (PLL). A 6x and a 1x clock

A 4pF sampling capacitor is used to sample the

are also output in LVDS format along with the data to

inputs. The choice of the external AC-coupling

enable easy data capture. The ADS5242 operates

capacitor is dictated by the attenuation at the lowest

from internally-generated reference voltages that are

desired input frequency of operation. The attenuation

trimmed to ensure matching across multiple devices

resulting from using a 10nF AC-coupling capacitor is

on a board. This feature eliminates the need for

0.04%.

external routing of reference lines and also improves

matching of the gain across devices. The nominal

values of REFT and REFB are 1.95V and 0.95V,

respectively. These values imply that a differential

input of –1V corresponds to the zero code of the

ADC, and a differential input of +1V corresponds to

the full-scale code (4095 LSB). VCM (common-mode

voltage of REFT and REFB) is also made available

externally through a pin, and is nominally 1.45V.

The ADC employs a pipelined converter architecture

consisting of a combination of multi-bit and single-bit

internal stages. Each stage feeds its data into the

digital

error

correction

logic,

ensuring

excellent

differential linearity and no missing codes at the

12-bit level. The pipeline architecture results in a data

latency of 6.5 clock cycles.

Figure 35. Analog Input Bias Circuitry

The output of the ADC goes to a serializer that

operates from a 12x clock generated by the PLL. The

12 data bits from each channel are serialized and

the

input

DC-coupled,

then

the

output

sent LSB first. In addition to serializing the data, the

common-mode voltage of the circuit driving the

serializer also generates a 1x clock and a 6x clock.

ADS5242 should match the VCM (which is provided as

These clocks are generated in the same way the

an output pin) to within

±50mV. It is recommended

serialized data is generated, so these clocks maintain

that the output common-mode of the driving circuit be

perfect synchronization with the data. The data and

derived from VCM provided by the device.

clock outputs of the serializer are buffered externally

using LVDS buffers. Using LVDS buffers to transmit

ADS5242IPAP Datasheet(PDF) 20 Page - Texas Instruments

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