ADS5242IPAP datasheet(12/29 Pages) TI

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ADS5242

SBAS330C – OCTOBER 2004 – REVISED OCTOBER 2005

PIN DESCRIPTIONS

NAME

PIN #

I/O

DESCRIPTION

ADCLK

Data Converter Clock Input

ADCLKN

Negative LVDS ADC Clock Output

ADCLKP

Positive LVDS ADC Clock Output

AVDD

1, 5, 10, 39, 44, 48, 55, 60

Analog Power Supply

AVSS

4, 6, 9, 40, 43, 45, 49, 57-59, 64

Analog Ground

Chip Select; 0 = Select, 1 = No Select

IN1N

Channel 1 Differential Analog Input Low

IN1P

Channel 1 Differential Analog Input High

IN2N

Channel 2 Differential Analog Input Low

IN2P

Channel 2 Differential Analog Input High

IN3N

Channel 3 Differential Analog Input Low

IN3P

Channel 3 Differential Analog Input High

IN4N

Channel 4 Differential Analog Input Low

IN4P

Channel 4 Differential Analog Input High

INT/EXT

Internal/External Reference Select; 0 = External, 1 = Internal. Weak pull-up to supply.

ISET

I/O

Bias Current Setting Resistor of 56.2k

Ω to Ground

LCLKN

Negative LVDS Clock

LCLKP

Positive LVDS Clock

LVDD

21, 27

LVDS Power Supply

LVSS

11, 13, 14, 22, 28, 35, 36, 38

LVDS Ground

17, 18, 31, 32

—

No Connection

OUT1N

Channel 1 Negative LVDS Data Output

OUT1P

Channel 1 Positive LVDS Data Output

OUT2N

Channel 2 Negative LVDS Data Output

OUT2P

Channel 2 Positive LVDS Data Output

OUT3N

Channel 3 Negative LVDS Data Output

OUT3P

Channel 3 Positive LVDS Data Output

OUT4N

Channel 4 Negative LVDS Data Output

OUT4P

Channel 4 Positive LVDS Data Output

Power-Down; 0 = Normal, 1 = Power-Down. Weak pull-down to ground.

REFB

I/O

Reference Bottom Voltage (2

Ω resistor in series with a capacitor ≥ 0.1µF to ground)

REFT

I/O

Reference Top Voltage (2

Ω resistor in series with a capacitor ≥ 0.1µF to ground)

RESET

Reset to Default; 0 = Reset, 1 = Normal. Weak pull-down to ground.

SCLK

Serial Data Clock

SDA

Serial Data Input

VCM

Common-Mode Output Voltage

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