ADS5242IPAP datasheet(23/29 Pages) TI

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LVDS BUFFERS

NOISE COUPLING ISSUES

External

Termination

Resistor

OUT

High

Low

OUT

Low

High

ADS5242

SBAS330C – OCTOBER 2004 – REVISED OCTOBER 2005

however, is determined by the rising edge of the

serializer is 780Mbps. The data comes out LSB first,

external clock and is not affected by jitter in the PLL.

with a register programmability that allows it to revert

In addition to generating a 50% duty cycle clock for

to MSB first. The serializer also transmits a 1x clock

the ADC, the PLL also generates a 12x clock that is

and

clock.

The

clock

(denoted

used by the serializer to convert the parallel data from

LCLKP/LCLKN) is meant to synchronize the capture of

the ADC to a serial stream of bits.

the LVDS data.

The use of the PLL automatically dictates the

Deskew mode can be enabled as well, using a

minimum sample rate to be about 20MSPS. The PLL

also requires the input clock to be free-running. If the

alternate 0s and 1s and can be used determine the

input clock is momentarily stopped (for a duration of

relative delay between the 6x clock and the output

less than 300ns) then the PLL would require

data for optimum capture. A 1x clock is also

approximately 10

µs to lock back to the input clock

generated by the serializer and transmitted through

frequency.

the LVDS buffer. The 1x clock (referred to as

ADCLKP/ADCLKN) is used to determine the start of

the 12-bit data frame. Sync mode (enabled through a

The LVDS buffer has two current sources, as shown

six 1s. Using this mode, the 1x clock can be used to

in Figure 38. OUTP and OUTN are loaded externally

determine the start of the data frame. In addition to

by a resistive load that is ideally about 100

Ω.

the deskew mode pattern and the sync mode pattern,

Depending on whether the data is 0 or 1, the currents

a custom pattern can be defined by the user and

are directed in one direction or the other through the

output from the LVDS buffer. The LVDS buffers are

resistor. The LVDS buffer has four current settings.

tri-stated in the power-down mode. The LVDS outputs

The default current setting is 3.5mA, and provides a

are weakly forced to 1.2V through 10k

Ω resistors

differential drop of about

±350mV across the 100Ω

(from each output pin to 1.2V).

resistor.

The single-ended output impedance of the LVDS

drivers is very high because they are current-source

High-speed mixed signals are sensitive to various

driven. If there are excessive reflections from the

types of noise coupling. One of the main sources of

receiver, it might be necessary to place a 100

Ω

noise is the switching noise from the serializer and

termination resistor across the outputs of the LVDS

the output buffers. Maximum care is taken to isolate

drivers to minimize the effect of reflections. In such a

these noise sources from the sensitive analog blocks.

situation, the output current of the LVDS drivers can

As a starting point, the analog and digital domains of

be increased to regain the output swing.

the chip are clearly demarcated. AVDD and AVSS

are used to denote the supplies for the analog

sections, while LVDD and LVSS are used to denote

the digital supplies. Care is taken to ensure that there

is minimal interaction between the supply sets within

the

device.

The

extent

noise

coupled

and

transmitted from the digital to the analog sections

depends on the following:

1. The

effective

inductances

each

the

supply/ground sets.

2. The isolation between the digital and analog

supply/ground sets.

Smaller effective inductance of the supply/ground

pins leads to better suppression of the noise. For this

reason,

multiple

pins

are

used

drive

each

supply/ground. It is also critical to ensure that the

impedances of the supply and ground lines on board

are kept to the minimum possible values. Use of

ground planes in the board as well as large

Figure 38. LVDS Buffer

decoupling

capacitors

between

the

supply

and

ground lines are necessary to get the best possible

SNR from the device.

The LVDS buffer receives data from a serializer that

takes the output data from each channel and

serializes it into a single data stream. For a clock

frequency of 65MHz, the data rate output of the

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