FXLS93333 datasheet(112/254 Pages) NXP

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NXP Semiconductors

FXLS9xxxx

Dual channel inertial sensor

aaa-030612

time

oscillator

adjustment

Response

one PSI5 period

Command

tPDCM_CMD_B

4 ms = nPDCM_PER_4ms_TYP

nOSC_4ms

new oscillator

count starts

Figure 18. PSI5 oscillator training timing diagram

Notes:

• In order to benefit from the PSI5 oscillator training accuracy improvements, the

oscillator must be trained prior to data transmissions in Initialization phase 2. For this

reason, if oscillator training is enabled in PSI5 mode, the device will not respond to

sync pulses during initialization phase 1, but oscillator training will be enabled tRS_PM

after reset.

11.5.1.3 SPI oscillator training

Oscillator training is enabled if the CK_CAL_EN bit is set in the TIMING_CFG register

and is accomplished by verifying the timing of periodic SOURCEID_0 sensor data

request SPI commands from the master against the value stored in the PDC-M_PER[2:0]

bits of the user read/write register array. The master programs the intended command

period into the PDC-M_PER[2:0] bits. The device then calculates the number of

transmission periods for every 4 ms (nSPI_PER_4ms_TYP).

In SPI Mode, oscillator training is completed over 4 ms periods if the CK_CAL_EN bit is

set. The following procedure is used to train the oscillator:

1. The device counts the number of oscillator cycles in nSPI_PER_4ms_TYP periods

(nOSC_4ms).

2. nOSC_4ms is compared to nOSC_4ms_TYP. If the value is within the acceptable training

window (OscTrainWIN) specified in Section 10.20, an oscillator adjustment is made.

Otherwise, no adjustment is made.

a. If nOSC_4ms is greater than nOSC_4ms_TYP + OscTrainADJ, the oscillator frequency

target is decreased by OscTrainRES.

b. If nOSC_4ms is less than nOSC_4ms_TYP - OscTrainADJ, the oscillator frequency target

is increased by OscTrainRES.

c. The oscillator frequency target value is changed.

11.5.1.4 I2C oscillator training

Oscillator training is enabled if the CK_CAL_EN bit is set in the TIMING_CFG register

and is accomplished by verifying the timing of periodic I2C reads of the SNSDATA0_L

read/write register array. The master programs the intended command period into the

PDCM_PER[2:0] bits. The device then calculates the number of transmission periods for

every 4 ms (nSPI_PER_4ms_TYP).

In I2C mode, oscillator training is completed over 4 ms periods if the CK_CAL_EN bit is

set. The following procedure is used to train the oscillator:

FXLS9xxxx

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Product data sheet

Rev. 6 — 8 February 2021

112 / 254

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