FXLS93333 datasheet(110/254 Pages) NXP

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NXP Semiconductors

FXLS9xxxx

Dual channel inertial sensor

11.5.1.1 DSI3 oscillator training

Oscillator training is enabled if the CK_CAL_EN bit is set in the TIMING_CFG register

and is accomplished by verifying the timing of periodic transmissions from the master

against the values stored in the CRM_PER[1:0] and PDCM_PER[2:0] bits of the user

read/write register array. The master programs the intended Periodic Data Collection

Mode command period into the PDCM_PER[2:0] bits and the intended Command

and Response Mode command period into the CRM_PER[1:0] bits. The device then

calculates the number of transmission periods for every 4 ms (nCRM_PER_4ms_TYP and

nPDCM_PER_4ms_-TYP).

In Command and Response Mode, oscillator training is completed over 4 ms periods

if and only if the CK_CAL_EN bit is set and the Command and Response Mode period

is between 500 µs and 4 ms, inclusive. The following procedure is used to train the

oscillator (See Figure 16):

1. The device counts the number of oscillator cycles in nCRM_PER_4ms_TYP periods

(nOSC_4ms).

2. nOSC_4ms is compared to nOSC_4ms_TYP. If the value is within the acceptable training

window (OscTrainWIN) specified in Section 10.20, an oscillator adjustment is made.

Otherwise, no adjustment is made.

a. If nOSC_4ms is greater than nOSC_4ms_TYP + OscTrainADJ, the oscillator frequency

target is decreased by OscTrainRES.

b. If nOSC_4ms is less than nOSC_4ms_TYP - OscTrainADJ, the oscillator frequency target

is increased by OscTrainRES.

c. The oscillator frequency target value is changed at the end of the command

blocking time for the command ending the nCRM_PER_OSC calculation.

If the CK_CAL_EN bit is cleared after oscillator training has already been initiated,

the state of the oscillator is determined by the state of the CK_CAL_RST bit in the

TIMING_CFG register. If the CK_CAL_RST bit is cleared, the last adjustment value for

the oscillator is maintained. If the CK_CAL_RST bit is set, the oscillator is reset to its

untrained value with the untrained tolerance specified in Section 10.20.

aaa-030610

time

oscillator

adjustment

Response

one CRM period

Command

tCmdBlock_CRM

4 ms = nCRM_PER_4ms_TYP

nOSC_4ms

new oscillator

count starts

Figure 16. Command and response mode oscillator training timing diagram

In Periodic Data Collection Mode, oscillator training is completed over 4 ms periods if

the CK_CAL_EN bit is set. The following procedure is used to train the oscillator (See

Figure 17):

1. The device counts the number of oscillator cycles in nPDCM_PER_4ms_TYP periods

(nOSC_4ms).

FXLS9xxxx

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Product data sheet

Rev. 6 — 8 February 2021

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