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FXLS93333 Datasheet(PDF) 107 Page - NXP Semiconductors |
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FXLS93333 Datasheet(HTML) 107 Page - NXP Semiconductors |
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107 / 254 page  NXP Semiconductors FXLS9xxxx Dual channel inertial sensor of these capacitors. A monitor circuit is incorporated to ensure predict-able operation if the connection to the external VBUF capacitor becomes open. If the external capacitor is not present, the regulator voltage will fall below the threshold specified in Section 10.4 causing the VBUF_ERR bit to be set in the DEVSTAT1 register. The VBUF capacitor is tested synchronous to the protocol transmissions as shown in the diagrams in Figure 12, Figure 13, and Figure 14. 11.4.1.1 VBUF capacitance monitor timing, DSI3 aaa-030606 tD_CAPTEST tD_CAPTEST tCAPTST_TIME tCAPTST_TIME capacitor present capacitor open time BUS_I Cap_Test VBUF VBUF_UV_f VBUF_ERR Figure 12. VBUF capacitor monitor timing, DSI3 11.4.1.2 VBUF capacitance monitor timing, PSI5 aaa-030607 tP_CAPTEST tP_CAPTEST tCAPTST_TIME tCAPTST_TIME capacitor present capacitor open time BUS_I Cap_Test VBUF VBUF_UV_f VBUF_ERR Figure 13. VBUF capacitor monitor timing, PSI5 synchronous mode FXLS9xxxx All information provided in this document is subject to legal disclaimers. © NXP B.V. 2021. All rights reserved. Product data sheet Rev. 6 — 8 February 2021 107 / 254 |
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