DS2148 datasheet(13/73 Pages) MAXIM

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DS2148/DS21Q48

13 of 73

NAME

I/O

FUNCTION

RNEG

Receive Negative Data. Updated on the rising edge (CCR2.0 = 0) or the

falling edge (CCR2.0 = 1) of RCLK with the bipolar data out of the line

interface. Set NRZE (CCR1.6) to a one for NRZ applications. In NRZ

mode, data will be output on RPOS while a received error will cause a

positive-going pulse synchronous with RCLK at RNEG. See Section 6.4

for details.

RPOS

Receive Positive Data. Updated on the rising edge (CCR2.0 = 0) or the

falling edge (CCR2.0 = 1) of RCLK with bipolar data out of the line

interface. Set NRZE (CCR1.6) to a one for NRZ applications. In NRZ

mode, data will be output on RPOS while a received error will cause a

positive-going pulse synchronous with RCLK at RNEG. See Section 6.2

for details.

RTIP/RRING

27/28

Receive Tip and Ring. Analog inputs for clock recovery circuitry. These

pins connect via a 1:1 transformer to the line. See Section 5 for details.

TCLK

Transmit Clock. A 2.048MHz or 1.544MHz primary clock. Used to clock

data through the transmit side formatter. Can be sourced internally by

MCLK or RCLK. See Common Control Register 1 and Figure 1-3.

TEST

Tri-state Control. Set high to tri-state all outputs and I/O pins (including

the parallel control port). Set low for normal operation. Useful in board

level testing.

TNEG

Transmit Negative Data. Sampled on the falling edge (CCR2.1 = 0) or

the rising edge (CCR2.1 = 1) of TCLK for data to be transmitted out onto

the line.

TPOS

Transmit Positive Data. Sampled on the falling edge (CCR2.1 = 0) or the

rising edge (CCR2.1 = 1) of TCLK for data to be transmitted out onto the

line.

TTIP/TRING

34/37

Transmit Tip and Ring. Analog line driver outputs. These pins connect

via a step-up transformer to the line. See Section 5 for details.

VDD

21/36

5.0V ±5% Positive Supply

VSM

Voltage Supply Mode. Should be tied high for 5V operation

VSS

22/35

Signal Ground

(R/

Active-Low Write Input (Read/Write). See the bus timing diagrams in

Section 10.

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