DS2148 datasheet(29/73 Pages) MAXIM

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DS2148/DS21Q48

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Table 4-1. MCLK Selection

MCLK

JAMUX

(CCR1.3)

ETS

(CCR1.7)

2.048MHz

1.544MHz

CCR2 (01H): COMMON CONTROL REGISTER 2

(MSB)

(LSB)

P25S

N/A

SCLD

CLDS

RHBE

THBE

TCES

RCES

SYMBOL

POSITION

DESCRIPTION

P25S

CCR2.7

Pin 25 Select. Forced to logic 0 in hardware mode.

0 = toggles high during a Receive Carrier Loss condition

1 = toggles high if TCLK does not transition for at least 5

µs.

CCR2.6

Not Assigned. Should be set to zero when written to.

SCLD

CCR2.5

Short Circuit Limit Disable (ETS = 0). Controls the 50mA

(RMS) current limiter.

0 = enable 50mA current limiter

1 = disable 50mA current limiter

CLDS

CCR2.4

Custom Line Driver Select. Setting this bit to a one will

redefine the operation of the transmit line driver. When this bit

is set to a one and CCR4.5 = CCR4.6 = CCR4.7 = 0, then the

device will generate a square wave at the TTIP and TRING

outputs instead of a normal waveform. When this bit is set to a

one and CCR4.5 = CCR4.6 = CCR4.7

≠ 0, then the device will

force TTIP and TRING outputs to become open drain drivers

instead of their normal push-pull operation. This bit should be

set to zero for normal operation of the device. Contact the

factory for more details on how to use this bit.

RHBE

CCR2.3

Receive HDB3/B8ZS Enable. See Figure 1-2.

0 = enable HDB3 (E1)/B8ZS (T1)

1 = disable HDB3 (E1)/B8ZS (T1)

THBE

CCR2.2

Transmit HDB3/B8ZS Enable. See Figure 1-3.

0 = enable HDB3 (E1)/B8ZS (T1)

1 = disable HDB3 (E1)/B8ZS (T1)

TCES

CCR2.1

Transmit Clock Edge Select. Selects which TCLK edge to

sample TPOS and TNEG. See Figure 1-3.

0 = sample TPOS and TNEG on falling edge of TCLK

1 = sample TPOS and TNEG on rising edge of TCLK

RCES

CCR2.0

Receive Clock Edge Select. Selects which RCLK edge to

update RPOS and RNEG. See Figure 1-2.

0 = update RPOS and RNEG on rising edge of RCLK

1 = update RPOS and RNEG on falling edge of RCLK

DS2148 Datasheet(PDF) 29 Page - Maxim Integrated Products

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