SLG46585M datasheet(67/210 Pages) DIALOG

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Datasheet

18-Sep-2019

CFR0011-120-00

Revision 3.3

67 of 210

SLG46585

GreenPAK Programmable Mixed-Signal Matrix with Asynchronous

State Machine, LDOs, and DC/DC Converter

7.3 3-BIT LUT OR PIPE DELAY/RIPPLE COUNTER MACROCELL

There is one macrocell that can serve as either a 3-bit LUT or as a Pipe Delay/Ripple Counter.

When used to implement LUT functions, the 3-bit LUT takes in three input signals from the connection matrix and produces a

single output, which goes back into the connection matrix.

When used as a Pipe Delay, there are three inputs signals from the matrix, Input (IN), Clock (CLK), and Reset (RST). The Pipe

Delay cell is built from 16 D Flip-Flop logic cells that provide the three delay options, two of which are user selectable. The DFF

cells are tied in series where the output (Q) of each delay cell goes to the next DFF cell input (IN). Both of the two outputs (OUT0

and OUT1) provide user selectable options for 1 – 16 stages of delay. There are delay output points for each set of the OUT0 and

OUT1 outputs to a 16-input MUX that is controlled by registers [1227:1224] for OUT0 and registers [1231:1228] for OUT1. The

16-input MUX is used to select the amount of delay.

Figure 20: DFF Polarity Operations with nSet

VDD

Data

Clock

POR

nSet (Case 1)

Q with nSet (Case 2)

Initial Polarity: High

Initial Polarity: Low

nSet (Case 1)

Q with nSet (Case 1)

nSet (Case 2)

Q with nSet (Case 2)

Q with nSet (Case 1)

nSet (Case 2)

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