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IMX6SDLCEC Datasheet(PDF) 153 Page - NXP Semiconductors |
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IMX6SDLCEC Datasheet(HTML) 153 Page - NXP Semiconductors |
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153 / 169 page  Package Information and Contact Assignments i.MX 6Solo/6DualLite Applications Processors for Consumer Products, Rev. 9, 11/2018 NXP Semiconductors 153 SD4_CLK E16 NVCC_NANDF GPIO ALT5 GPIO7_IO10 Input 100 k Ω pull-up SD4_CMD B17 NVCC_NANDF GPIO ALT5 GPIO7_IO09 Input 100 k Ω pull-up SD4_DAT0 D18 NVCC_NANDF GPIO ALT5 GPIO2_IO08 Input 100 k Ω pull-up SD4_DAT1 B19 NVCC_NANDF GPIO ALT5 GPIO2_IO09 Input 100 k Ω pull-up SD4_DAT2 F17 NVCC_NANDF GPIO ALT5 GPIO2_IO10 Input 100 k Ω pull-up SD4_DAT3 A20 NVCC_NANDF GPIO ALT5 GPIO2_IO11 Input 100 k Ω pull-up SD4_DAT4 E18 NVCC_NANDF GPIO ALT5 GPIO2_IO12 Input 100 k Ω pull-up SD4_DAT5 C19 NVCC_NANDF GPIO ALT5 GPIO2_IO13 Input 100 k Ω pull-up SD4_DAT6 B20 NVCC_NANDF GPIO ALT5 GPIO2_IO14 Input 100 k Ω pull-up SD4_DAT7 D19 NVCC_NANDF GPIO ALT5 GPIO2_IO15 Input 100 k Ω pull-up TAMPER E11 VDD_SNVS_IN GPIO ALT0 SNVS_TAMPER Input 100 k Ω pull-down TEST_MODE E12 VDD_SNVS_IN GPIO ALT0 TCU_TEST_MODE Input 100 k Ω pull-down USB_H1_DN F10 VDDUSB_CAP — — USB_H1_DN — — USB_H1_DP E10 VDDUSB_CAP — — USB_H1_DP — — USB_OTG_CHD_B B8 VDDUSB_CAP — — USB_OTG_CHD_B — — USB_OTG_DN B6 VDDUSB_CAP — — USB_OTG_DN — — USB_OTG_DP A6 VDDUSB_CAP — — USB_OTG_DP — — XTALI A7 NVCC_PLL_OUT — — XTALI — — XTALO B7 NVCC_PLL_OUT — — XTALO — — 1 The state immediately after reset and before ROM firmware or software has executed. 2 Variance of the pull-up and pull-down strengths are shown in the tables as follows: • Table 23, "GPIO DC Parameters," on page 40 • Table 24, "LPDDR2 I/O DC Electrical Parameters," on page 41 • Table 25, "DDR3/DDR3L I/O DC Electrical Characteristics," on page 42 3 ENET_REF_CLK is used as a clock source for MII and RGMII modes only. RGMII mode uses either GPIO_16 or RGMII_TX_CTL as a clock source. For more information on these clocks, see the device Reference Manual and the Hardware Development Guide for i.MX 6Quad, 6Dual, 6DualLite, 6Solo Families of Applications Processors (IMX6DQ6SDLHDG). Table 98. Signals with Differing Before Reset and After Reset States Ball Name Before Reset State Input/Output Value EIM_A16 Input PD (100K) EIM_A17 Input PD (100K) EIM_A18 Input PD (100K) EIM_A19 Input PD (100K) Table 97. 21 x 21 mm Functional Contact Assignments (continued) Ball Name Ball Power Group Ball Type Out of Reset Condition1 Default Mode (Reset Mode) Default Function Input/ Output Value2 |
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