IMX6SDLCEC datasheet(47/169 Pages) NXP

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Electrical Characteristics

i.MX 6Solo/6DualLite Applications Processors for Consumer Products, Rev. 9, 11/2018

NXP Semiconductors

Table 32 shows the AC parameters for DDR I/O operating in DDR3/DDR3L mode.

4.7.3

LVDS I/O AC Parameters

The differential output transition time waveform is shown in Figure 7.

Figure 7. Differential LVDS Driver Transition Time Waveform

Table 33 shows the AC parameters for LVDS I/O.

3 The typical value of Vix(ac) is expected to be about 0.5 x OVDD. and Vix(ac) is expected to track variation of OVDD. Vix(ac)

indicates the voltage at which differential input signal must cross.

Table 32. DDR I/O DDR3/DDR3L Mode AC Parameters1

1 Note that the JEDEC JESD79_3C specification supersedes any specification in this document.

Parameter

Symbol

Test Condition

Min

Typ

Max

Unit

AC input logic high

Vih(ac)

—

Vref + 0.175

—

OVDD

AC input logic low

Vil(ac)

—

Vref - 0.175

AC differential input voltage2

2 Vid(ac) specifies the input differential voltage | Vtr-Vcp | required for switching, where Vtr is the “true” input signal and Vcp is

the “complementary” input signal. The Minimum value is equal to Vih(ac) - Vil(ac).

Vid(ac)

—

0.35

—

Input AC differential cross point voltage3, 4

3 The typical value of Vix(ac) is expected to be about 0.5 x OVDD. and Vix(ac) is expected to track variation of OVDD. Vix(ac)

indicates the voltage at which differential input signal must cross.

4 Extended range for Vix is only allowed for the clock and when the single-ended clock input signals CK and CK# are:

• monotonic with a single-ended swing VSEL/VSEH of at least VDD/2

±250 mV, and

• the differential slew rate of CK - CK# is larger than 3 V/ns

Vix(ac)

Relative to Vref

Vref - 0.15

—

Vref + 0.15

Over/undershoot peak

Vpeak

—

0.4

Over/undershoot area (above OVDD

or below OVSS)

Varea

400 MHz

—

0.5

V-ns

Single output slew rate, measured between

Vol(ac) and Voh(ac)

tsr

Driver impedance = 34

2.5

—

V/ns

Skew between pad rise/fall asymmetry + skew

caused by SSN

tSKD

clk = 400 MHz

——

0.1

padp

padn

VDIFF

0V (Differential)

VDIFF = {padp} - {padn}

tTLH

20%

80%

20%

80%

tTHL

VOH

VOL

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