IMX6SDLCEC datasheet(71/169 Pages) NXP

71 / 169 page

Electrical Characteristics

i.MX 6Solo/6DualLite Applications Processors for Consumer Products, Rev. 9, 11/2018

NXP Semiconductors

Figure 35. Samsung Toggle Mode Data Read Timing

Table 48. Samsung Toggle Mode Timing Parameters1

Parameter

Symbol

Timing

T = GPMI Clock Cycle

Unit

Min

Max

NF1

NAND_CLE setup time

tCLS

(AS + DS)

× T - 0.12 [see 2,3]

NF2

NAND_CLE hold time

tCLH

× T - 0.72 [see 2]

NF3

NAND_CE0_B setup time

tCS

(AS + DS)

× T - 0.58 [see 3,2]

NF4

NAND_CE0_B hold time

tCH

× T - 1 [see 2]

NF5

NAND_WE_B pulse width

tWP

× T [see 2]

NF6

NAND_ALE setup time

tALS

(AS + DS)

× T - 0.49 [see 3,2]

NF7

NAND_ALE hold time

tALH

× T - 0.42 [see 2]

NF8

Command/address NAND_DATAxx setup time

tCAS

× T - 0.26 [see 2]

NF9

Command/address NAND_DATAxx hold time

tCAH

× T - 1.37 [see 2]

NF18 NAND_CEx_B access time

tCE

CE_DELAY

× T [see 4,2]—

NF22 clock period

tCK

—

NF23 preamble delay

tPRE

PRE_DELAY

× T [see 5,2]—

NF24 postamble delay

tPOST

POST_DELAY

× T +0.43 [see 2]—

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