IMX6SDLCEC datasheet(86/169 Pages) NXP

86 / 169 page

i.MX 6Solo/6DualLite Applications Processors for Consumer Products, Rev. 9, 11/2018

NXP Semiconductors

Electrical Characteristics

Figure 48. RGMII Transmit Signal Timing Diagram Original

Figure 49. RGMII Receive Signal Timing Diagram Original

Table 60. RGMII Signal Switching Specifications1

1 The timings assume the following configuration:

DDR_SEL = (11)b

DSE (drive-strength) = (111)b

Symbol

Description

Min

Max

Unit

Tcyc

2 For 10 Mbps and 100 Mbps, T

cyc will scale to 400 ns ±40 ns and 40 ns ±4 ns respectively.

Clock cycle duration

7.2

8.8

TskewT

3 For all versions of RGMII prior to 2.0; This implies that PC board design will require clocks to be routed such that an additional

trace delay of greater than 1.5 ns and less than 2.0 ns will be added to the associated clock signal. For 10/100, the Max value

is unspecified.

Data to clock output skew at transmitter

-500

500

TskewR

Data to clock input skew at receiver

2.6

Duty_G4

4 Duty cycle may be stretched/shrunk during speed changes or while transitioning to a received packet's clock domain as long

as minimum duty cycle is not violated and stretching occurs for no more than three Tcyc of the lowest speed transitioned

between.

Duty cycle for Gigabit

Duty_T4

Duty cycle for 10/100T

Tr/Tf

Rise/fall time (20–80%)

—

0.75

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