IMX6SDLCEC datasheet(51/169 Pages) NXP

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Electrical Characteristics

i.MX 6Solo/6DualLite Applications Processors for Consumer Products, Rev. 9, 11/2018

NXP Semiconductors

Table 36 shows the GPIO output buffer impedance (OVDD 3.3 V).

4.8.2

DDR I/O Output Buffer Impedance

For details on supported DDR memory configurations, see Section 4.9.4, “Multi-Mode DDR Controller

(MMDC).

Table 37 shows DDR I/O output buffer impedance of i.MX 6Solo/6DualLite processors.

Note:

1. Output driver impedance is controlled across PVTs using ZQ calibration procedure.

2. Calibration is done against 240

Ω external reference resistor.

3. Output driver impedance deviation (calibration accuracy) is ±5% (max/min impedance) across PVTs.

4.8.3

LVDS I/O Output Buffer Impedance

The LVDS interface complies with TIA/EIA 644-A standard. See, TIA/EIA STANDARD 644-A,

“Electrical Characteristics of Low Voltage Differential Signaling (LVDS) Interface Circuits” for details.

Table 36. GPIO Output Buffer Average Impedance (OVDD 3.3 V)

Parameter

Symbol

Drive Strength (DSE)

Typ Value

Unit

Output Driver

Impedance

Rdrv

001

010

011

100

101

110

111

150

Table 37. DDR I/O Output Buffer Impedance

Parameter

Symbol

Test Conditions DSE

(Drive Strength)

Typical

Unit

NVCC_DRAM=1.5 V

(DDR3)

DDR_SEL=11

NVCC_DRAM=1.2 V

(LPDDR2)

DDR_SEL=10

Output Driver

Impedance

Rdrv

000

001

010

011

100

101

110

111

Hi-Z

240

120

Hi-Z

240

120

IMX6SDLCEC Datasheet(PDF) 51 Page - NXP Semiconductors

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