IMX6SDLCEC datasheet(94/169 Pages) NXP

94 / 169 page

i.MX 6Solo/6DualLite Applications Processors for Consumer Products, Rev. 9, 11/2018

NXP Semiconductors

Electrical Characteristics

4.11.10.2 Sensor Interface Timings

There are three camera timing modes supported by the IPU.

4.11.10.2.1 BT.656 and BT.1120 Video Mode

Smart camera sensors, which include imaging processing, usually support video mode transfer. They use

an embedded timing syntax to replace the IPUx_CSIx_VSYNC and IPUx_CSIx_HSYNC signals. The

timing syntax is defined by the BT.656/BT.1120 standards.

This operation mode follows the recommendations of ITU BT.656/ ITU BT.1120 specifications. The only

control signal used is IPUx_CSIx_PIX_CLK. Start-of-frame and active-line signals are embedded in the

data stream. An active line starts with a SAV code and ends with a EAV code. In some cases, digital

blanking is inserted in between EAV and SAV code. The CSI decodes and filters out the timing-coding

from the data stream, thus recovering IPUx_CSIx_VSYNC and IPUx_CSIx_HSYNC signals for internal

use. On BT.656 one component per cycle is received over the IPUx_CSIx_DATA_EN bus. On BT.1120

two components per cycle are received over the IPUx_CSIx_DATA_EN bus.

IPUx_CSIx_

DATA13

B[1], G[4]

R[3],G[5],B[3]

R/G/B[5]

R/G/B[1]

Y/C[1]

G[4]

Y[1]

Y[3]

IPUx_CSIx_

DATA14

B[2], G[5]

R[4],G[0],B[4]

R/G/B[0]

R/G/B[2]

Y/C[2]

G[5]

Y[2]

Y[4]

IPUx_CSIx_

DATA15

B[3], R[0]

R[0],G[1],B[0]

R/G/B[1]

R/G/B[3]

Y/C[3]

R[0]

Y[3]

Y[5]

IPUx_CSIx_

DATA16

B[4], R[1]

R[1],G[2],B[1]

R/G/B[2]

R/G/B[4]

Y/C[4]

R[1]

Y[4]

Y[6]

IPUx_CSIx_

DATA17

G[0], R[2]

R[2],G[3],B[2]

R/G/B[3]

R/G/B[5]

Y/C[5]

R[2]

Y[5]

Y[7]

IPUx_CSIx_

DATA18

G[1], R[3]

R[3],G[4],B[3]

R/G/B[4]

R/G/B[6]

Y/C[6]

R[3]

Y[6]

Y[8]

IPUx_CSIx_

DATA19

G[2], R[4]

R[4],G[5],B[4]

R/G/B[5]

R/G/B[7]

Y/C[7]

R[4]

Y[7]

Y[9]

1 IPUx_CSIx stands for IPUx_CSI0 or IPUx_CSI1.

2 The MSB bits are duplicated on LSB bits implementing color extension.

3 The two MSB bits are duplicated on LSB bits implementing color extension.

4 YCbCr, 8 bits—Supported within the BT.656 protocol (sync embedded within the data stream).

5 RGB 16 bits—Supported in two ways: (1) As a “generic data” input, with no on-the-fly processing; (2) With on-the-fly

processing, but only under some restrictions on the control protocol.

6 YCbCr 16 bits—Supported as a “generic-data” input, with no on-the-fly processing.

7 YCbCr 16 bits—Supported as a sub-case of the YCbCr, 20 bits, under the same conditions (BT.1120 protocol).

8 YCbCr, 20 bits—Supported only within the BT.1120 protocol (syncs embedded within the data stream).

Table 64. Camera Input Signal Cross Reference, Format, and Bits Per Cycle (continued)

Signal

Name1

RGB565

8 bits

2 cycles

RGB5652

8 bits

3 cycles

RGB6663

8 bits

3 cycles

RGB888

8 bits

3 cycles

YCbCr4

8 bits

2 cycles

RGB5655

16 bits

1 cycle

YCbCr6

16 bits

1 cycle

YCbCr7

16 bits

1 cycle

YCbCr8

20 bits

1 cycle

IMX6SDLCEC Datasheet(PDF) 94 Page - NXP Semiconductors

IMX6SDLCEC Datasheet(HTML) 94 Page - NXP Semiconductors

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL