IMX6SDLCEC datasheet(25/169 Pages) NXP

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Electrical Characteristics

i.MX 6Solo/6DualLite Applications Processors for Consumer Products, Rev. 9, 11/2018

NXP Semiconductors

4.1.2

Thermal Resistance

NOTE

Per JEDEC JESD51-2, the intent of thermal resistance measurements is

solely for a thermal performance comparison of one package to another in a

standardized environment. This methodology is not meant to and will not

predict the performance of a package in an application-specific

environment.

4.1.2.1

BGA Case 2240 Package Thermal Resistance

Table 7 displays the thermal resistance data.

Vin/Vout input/output voltage range (DDR pins)

Vin/Vout

-0.5

OVDD+0.4 (See notes 1 & 2)

ESD immunity (HBM)

Vesd_HBM

—

2000

ESD immunity (CDM)

Vesd_CDM

—500

Storage temperature range

Tstorage

-40

150

°C

1 The absolute maximum voltage includes an allowance for 400 mV of overshoot on the IO pins. Per JEDEC standards, the

allowed signal overshoot must be derated if NVCC_DRAM exceeds 1.575V.

2 OVDD is the I/O supply voltage.

Table 7. Thermal Resistance Data

Rating

Test Conditions

Symbol

Value

Unit

Junction to Ambient1

1 Junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site (board)

temperature, ambient temperature, air flow, power dissipation of other components on the board, and board thermal resistance.

Single-layer board (1s); natural convection2

Four-layer board (2s2p); natural convection2

2 Per JEDEC JESD51-2 with the single layer board horizontal. Thermal test board meets JEDEC specification for the specified

package.

RθJA

oC/W

Junction to Ambient1

Single-layer board (1s); airflow 200 ft/min2,3

Four-layer board (2s2p); airflow 200 ft/min2,3

3 Per JEDEC JESD51-6 with the board horizontal.

RθJA

oC/W

Junction to Board1,4

4 Thermal resistance between the die and the printed circuit board per JEDEC JESD51-8. Board temperature is measured on

the top surface of the board near the package.

—RθJB

oC/W

Junction to Case1,5

5 Thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC-883 Method

1012.1).

—RθJC

oC/W

Junction to Package Top1,6

6 Thermal characterization parameter indicating the temperature difference between package top and the junction temperature

per JEDEC JESD51-2. When Greek letters are not available, the thermal characterization parameter is written as Psi-JT.

Natural convection

ΨJT

oC/W

Table 6. Absolute Maximum Ratings (continued)

Parameter Description

Symbol

Min

Max

Unit

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