IMX6SDLCEC datasheet(163/169 Pages) NXP

163 / 169 page

Revision History

i.MX 6Solo/6DualLite Applications Processors for Consumer Products, Rev. 9, 11/2018

NXP Semiconductors

163

Revision History

Table 101 provides the current revision history for this data sheet. Table 102 provides a revision history for

previous revisions.

Table 101. i.MX 6Solo/6DualLite Data Sheet Document Rev. 9 History

Rev.

Number

Date

Substantive Changes

10/2018 Changes to Revision 9 include the following:

• Table 3, "Special Signal Considerations," on page 21: Corrected,

– Row: NC, from “These signals are No Connected …” to read, “These signals are not functional and

must remain unconnected by the user.”

• Table 8, "Operating Ranges," on page 26: Corrected footnote 6:

– Changed from: “When VDD_SOC_IN does not supply… then maximum setting can be 1.3V.”

– Changed to: “When using VDD_SOC_CAP to supply the PCIE_VP and PCIE_VPTX, the maximum

setting is 1.175V. …”

• Table 53, "eMMC4.4/4.41 Interface Timing Specification," on page 80,

– Row: SD2, uSDHC Output Delay: Changed tOD from 2.5ns minimum to 2.8ns and 7.1ns maximum to

6.8ns.

• Table 96, "21 x 21 mm Supplies Contact Assignments," on page 140: Corrected,

– Last row: NC, from “—” to read, These signals are not functional and must remain unconnected by the

user.

09/2017 • Replaced ipp_dse with DSE throughout.

• Section 1, “Introduction: Replaced text “low voltage DDR3” with “DDR3L” in the features list of i.MX

6Solo/6DualLite applications processors.

• Table 1, "Example Orderable Part Numbers," on page 3: Added orderable part numbers.

• Figure 1: Updated to include Rev 1.4 in Silicon Revision section.

• Section 2.1, “Block Diagram: Updated WEIM with EIM in the block diagram.

• Table 2, "i.MX 6Solo/6DualLite Modules List," on page 11: Rearranged alphabetically.

• Table 6, "Absolute Maximum Ratings," on page 24:

– Removed VDD_HIGH_IN supply voltage (LDO bypass) parameter.

– Max. value of VDD_HIGH_CAP supply output voltage corrected to 2.85V.

• Table 22: Updated test condition of “

XTALI input leakage current at startup” parameter; replaced 32KHz RTC

with 24MHz.

• Added Section 4.6.4, “RGMII I/O 2.5V I/O DC Electrical Parameters.

• Section 4.8.2, “DDR I/O Output Buffer Impedance: Modified introductory text.

• Corrected Figure 22, "Asynchronous A/D Muxed Write Access," on page 60.

• Table 53, "eMMC4.4/4.41 Interface Timing Specification," on page 80:

– Added the following footnote to Card Input Clock section: 1 Clock duty cycle will be in the range of 47% to

53%.

– Min. value of uSDHC Input Setup Time reduced to 1.7ns.

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