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ADSP-SC591 Datasheet(PDF) 83 Page - Analog Devices

Part # ADSP-SC591
Description  SHARC Dual-Core DSP with Arm Cortex-A5
PDF  143 Pages
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Manufacturer  AD [Analog Devices]
Direct Link  http://www.analog.com
Logo AD - Analog Devices

ADSP-SC591 Datasheet(HTML) 83 Page - Analog Devices

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 83 / 143 page
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Rev. PrD
|
Page 83 of 143
|
May 2021
ADSP-21591/21593/21594/ADSP-SC591/SC592/SC594
Preliminary Technical Data
Table 44. SPORTs—Internal Clock1
All specifications are based on simulation data and are subject to change without notice.
Parameter
Min
Max
Unit
Timing Requirements
tSFSI
Frame Sync Setup Before SPTx_CLK
(Externally Generated Frame Sync in Either Transmit or
Receive Mode)2
TBD
ns
tHFSI
Frame Sync Hold After SPTx_CLK
(Externally Generated Frame Sync in Either Transmit or
Receive Mode)2
TBD
ns
tSDRI
Receive Data Setup Before SPTx_CLK2
TBD
ns
tHDRI
Receive Data Hold After SPTx_CLK2
TBD
ns
Switching Characteristics
tDFSI
Frame Sync Delay After SPTx_CLK (Internally Generated
Frame Sync in Transmit or Receive Mode)3
TBD
ns
tHOFSI
Frame Sync Hold After SPTx_CLK (Internally Generated
Frame Sync in Transmit or Receive Mode)3
TBD
ns
tDDTI
Transmit Data Delay After SPTx_CLK3
TBD
ns
tHDTI
Transmit Data Hold After SPTx_CLK3
TBD
ns
tSPTCLKIW
SPTx_CLK Width4
0.5 × tSPTCLKPROG – TBD
ns
tSPTCLKW
SPTx_CLK Period4
tSPTCLKPROG – TBD
ns
1 Specifications apply to all four SPORTs.
2 Referenced to the sample edge.
3 Referenced to drive edge.
4 See Table 26 for details on the minimum period that can be programmed for fSPTCLKPROG.



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