DS1884 datasheet(34/92 Pages) MAXIM

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DS1884

SFP and PON ONU Controller

with Digital LDD Interface

Maxim Integrated

Power Leveling

The DS1884 supports power leveling as described in

G.984.2. The POW_LEV[1:0] bits in UPDATE A2h Lower

Memory, Register 6Fh allow for three power level set-

tings: 0dB, -3dB, and -6dB. Depending on the operation

mode, a combination of SET_IMOD and the KRMD bits

(MAX3710 TXCTRL3 register) are adjusted to meet these

power-level settings. The KRMD bits adjust the gain of

the APC loop and extinction ratio loop.

Manual MAX3710 Operations

The master interface is controllable using four registers

in the DS1884: 3WCTRL, ADDRESS, WRITE, READ.

Commands can be manually issued while the DS1884 is

in normal operation mode. It is also possible to suspend

normal 3-wire commands so that only manual operation

commands are sent (3WCTRL, A2h Table 04h, Register

F8h–FFh).

I2C Communication

I2C Definition

The following terminology is commonly used to describe

I2C data transfers.

Master Device: The master device controls the slave

devices on the bus. The master device generates SCL

clock pulses and START and STOP conditions.

Slave Devices: Slave devices send and receive data

at the master’s request.

Bus Idle or Not Busy: Time between STOP and

START conditions when both SDA and SCL are inac-

tive and in their logic-high states.

START Condition: A START condition is generated by

the master to initiate a new data transfer with a slave.

Transitioning SDA from high to low while SCL remains

high generates a START condition. See Figure 18 for

applicable timing.

STOP Condition: A STOP condition is generated

by the master to end a data transfer with a slave.

Transitioning SDA from low to high while SCL remains

high generates a STOP condition. See Figure 18 for

applicable timing.

Repeated START Condition: The master can use a

repeated START condition at the end of one data transfer

to indicate that it will immediately initiate a new data trans-

fer following the current one. Repeated STARTs are com-

monly used during read operations to identify a specific

memory address to begin a data transfer. A repeated

START condition is issued identically to a normal START

condition. See Figure 18 for applicable timing.

Bit Write: Transitions of SDA must occur during the

low state of SCL. The data on SDA must remain valid

and unchanged during the entire high pulse of SCL

plus the setup and hold time requirements (Figure 18).

Data is shifted into the device during the rising edge

of the SCL.

Bit Read: At the end a write operation, the master

must release the SDA bus line for the proper amount

of setup time before the next rising edge of SCL during

a bit read (Figure 18). The device shifts out each bit of

data on SDA at the falling edge of the previous SCL

pulse and the data bit is valid at the rising edge of the

current SCL pulse. Remember that the master gener-

ates all SCL clock pulses, including when it is reading

bits from the slave.

Table 13. Power Leveling Details

LOOP OPERATING

MODE

POWER LEVEL

(dB)

POW_LEV[1:0]

MODULATION CHANGE

KRMD[2:1]

(MAX3710)

Open Loop

None

-3

Right-shift value written to SET_IMOD once

-6

Right-shift value written to SET_IMOD twice

APC Loop

None

-3

Right-shift value written to SET_IMOD once

-6

Right-shift value written to SET_IMOD twice

Dual Closed Loop

None

-3

None

-6

None

DS1884 Datasheet(PDF) 34 Page - Maxim Integrated Products

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