Serial Interface Command Format

All communication commands into the MAX1455 follow the

format of a start bit, 8 command bits (command byte), and

a stop bit. The Command Byte controls the contents of the

IRS and comprises a 4-bit interface register set address

(IRSA) nibble and a 4-bit interface register set data (IRSD)

nibble. The IRS Command Byte is structured as follows:

IRS[7:0] = IRSD[3:0], IRSA[3:0]

All commands are transmitted LSB first. The first bit fol-

lowing the start bit is IRSA[0] and the last bit before the

stop is IRSD[3] as follows:

IRSA

IRSD

11111 0 01230 123 1 11 11 1

Half of the register contents of the IRS are used for data

hold and steering information. Data writes to two locations

within the IRS cause immediate action (command execu-

tion). These locations are at addresses 9 and 15 and are

the Command Register to Internal Logic (CRIL) and reini-

tialize commands, respectively. Table 9 shows a full listing

of IRS address decoding.

Command sequences can be written to the MAX1455

as a continuous stream, i.e., start bit, command byte,

stop bit, start bit, command byte, stop bit, etc. There are

no delay requirements between commands while the

MAX1455 is receiving data.

Command Register to Internal Logic

A data write to the CRIL location (IRS address 9) causes

immediate execution of the command associated with

the 4-bit data nibble written. All EEPROM and Calibration

register read and write, together with EEPROM erase,

commands are handled through the CRIL location. CRIL

is also used to enable the MAX1455 analog output and to

place output data (serial digital output) on DIO. Table 10

shows a full listing of CRIL commands.

Table 5. Configuration Register (CONFIG[15:0])

Table 6. PGA Gain Setting (PGA[3:0])

FIELD

NAME

DESCRIPTION

15:13

OSC[2:0]

Oscillator frequency setting.

Factory preset; do not change.

12:11

CLIP[1:0]

Sets output clip levels.

10

PGA Sign

Logic 1 inverts INM and INP polarity (Table 6).

9

IRO Sign

Logic 1 for positive input-referred offset (IRO). Logic 0 for negative IRO.

8:6

IRO[2:0]

Input-referred coarse-offset adjustment (Table 7).

5:2

PGA[3:0]

Programmable-gain amplifier setting.

1

ODAC Sign

Logic 1 for positive offset DAC output. Logic 0 for negative offset DAC output.

0

OTCDAC

Sign

Logic 1 for positive offset TC DAC output. Logic 0 for negative offset TC DAC output.

PGA[3:0]

PGA GAIN (V/V)

0000

39

0001

52

0010

65

0011

78

0100

91

0101

104

0110

117

0111

130

1000

143

1001

156

1010

169

1011

182

1100

195

1101

208

1110

221

1111

234

MAX1455

Low-Cost Precision Sensor Signal Conditioner

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