The MAX1455 internal clock controls timing functions,

including the signal path gain, DAC functions, and com-

munications. It is recommended that, while in digital

mode, the Configuration register CLK bits be assigned the

values contained in EEPROM (upper configuration byte).

The 3 CLK bits represent a two’s-complement number

with a nominal clock adjustment of 9% per bit. Table 12

shows the codes and adjustment available.

Any change to the CLK bit values contained in the

Configuration register must be followed by the MAX1455

baud rate learning sequence (reinitialize and initialize

commands). To maximize the robustness of the commu-

nication system during clock resetting only, change the

CLK bits by 1 LSB value at a time. The recommended set-

ting procedure for the Configuration register CLK bits is,

therefore, as follows. (Use a minimum baud rate of 9600

during the setting procedure to prevent potential overflow

of the MAX1455 baud rate counter with clock values near

maximum.)

The following example is based on a required CLK code

of 010 binary:

1) Read the CLK bits (3MSBs) from EEPROM location

161hex. CLK = 010 binary.

2) Set the CLK bits in the Configuration register to 001

binary.

3) Send the reinitialize command, followed by the initial-

ize (baud rate learning) command.

4) Set the CLK bits in the Configuration register to 010

binary.

5) Send the reinitialize command, followed by the initialize

(baud rate learning) command.

The frequency of the internal oscillator can be checked at

any time by reading the value of BITCLK[7:0]. This 8-bit

number represents the number of internal oscillator cycles

corresponding to 1 cycle (1 bit time) of the communica-

tions baud rate.

Table 8. Control Location (CL[15:0])

Table 9. IRSA Decoding

FIELD

NAME

DESCRIPTION

15:8

CL[15:8]

Reserved

7:0

CL[7:0]

Control Location. Secure-Lock is activated by setting this to FFhex, which disables DIO serial

communications and connects OUT to PGA output.

IRSA[3:0]

DESCRIPTION

0000

Write IRSD[3:0] to DHR[3:0] (Data Hold register)

0001

Write IRSD[3:0] to DHR[7:4] (Data Hold register)

0010

Write IRSD[3:0] to DHR[11:8] (Data Hold register)

0011

Write IRSD[3:0] to DHR[15:12] (Data Hold register)

0100

Reserved

0101

Reserved

0110

Write IRSD[3:0] to ICRA[3:0] or IEEA[3:0] (Internal Calibration register address or internal EEPROM

address nibble 0)

0111

Write IRSD[3:0] to IEEA[7:4] (internal EEPROM address, nibble 1)

1000

Write IRSD[3:0] to IRSP[3:0] or IEEA[9:8] (Interface register set pointer where IRSP[1:0] is IEEA[9:8])

1001

Write IRSD[3:0] to CRIL[3:0] (Command register to internal logic)

1010

Write IRSD[3:0] to ATIM[3:0] (analog timeout value on read)

1011

Write IRSD[3:0] to ALOC[3:0] (analog location)

1100 to 1110

Reserved

1111

Write IRSD[3:0] = 1111bin to relearn the baud rate

MAX1455

Low-Cost Precision Sensor Signal Conditioner

www.maximintegrated.com

Maxim Integrated │ 15